MC908MR32CFUE Datasheet, PDF (33/282 Pages) Freescale Semiconductor, Inc – Microcontrollers

Addr.
$003E
$003F
$0040
$0041
$0042
$0043
$0044
$0045
$0046
$0047
↓
$0050
Memory Map
Register Name
Bit 7
SCI Baud Rate Register ^{Read: 0}
(SCBR) Write: R
See page 177. _{Reset: 0}
IRQ Status/Control Register ^{Read: 0}
(ISCR) Write: R
See page 94. _{Reset: 0}
ADC Status and Control
Register (ADSCR)
See page 52.
Read:
Write:
Reset:
COCO
R
0
ADC Data Register High ^{Read: 0}
Right Justified Mode (ADRH) Write: R
See page 54. _Reset:
ADC Data Register Low ^{Read: AD7}
Right Justified Mode (ADRL) Write: R
See page 54. _Reset:
ADC Clock Register
(ADCLK)
See page 55.
Read:
Write:
Reset:
ADIV2
0
SPI Control Register
(SPCR)
See page 211.
Read:
Write:
Reset:
SPRIE
0
SPI Status and Control
Register (SPSCR)
See page 212.
Read:
Write:
Reset:
SPRF
R
0
SPI Data Register ^{Read: R7}
(SPDR) Write: T7
See page 214. _Reset:
6
5
4
3
0
0
SCP1 SCP0
R
R
0
0
0
0
0
0
0
IRQF
R
R
R
0
0
0
0
AIEN ADCO ADCH4 ADCH3
0
0
0
0
R
R
AD6
AD5
R
R
1
1
0
0
R
R
Unaffected by reset
AD4
AD3
R
R
Unaffected by reset
ADIV1 ADIV0 ADICLK MODE1
0
0
0
0
R SPMSTR CPOL
CPHA
0
ERRIE
0
R6
T6
1
OVRF
R
0
R5
T5
0
1
MODF
SPTE
R
R
0
1
R4
R3
T4
T3
Unaffected by reset
2
1
Bit 0
SCR2 SCR1 SCR0
0
0
ACK1
0
0
0
IMASK1 MODE1
0
0
ADCH2 ADCH1 ADCH0
1
1
1
0
AD9
AD8
R
R
R
AD2
AD1
AD0
R
R
R
MODE0
0
1
0
SPWOM SPE
0
0
MODFEN SPR1
0
0
R2
R1
T2
T1
0
R
0
SPTIE
0
SPR0
0
R0
T0
Unimplemented
$0051
TIMB Status/Control Register
(TBSC)
See page 244.
$0052
TIMB Counter Register High
(TBCNTH)
See page 246.
U = Unaffected X = Indeterminate
Read:
Write:
Reset:
Read:
Write:
Reset:
TOF
0
0
Bit 15
R
0
R
TOIE TSTOP
0
1
Bit 14 Bit 13
R
R
0
0
= Reserved
0
TRST
0
Bit 12
R
0
Bold
0
R
0
Bit 11
R
0
= Buffered
PS2
PS1
PS0
0
Bit 10
R
0
0
0
Bit 9
Bit 8
R
R
0
0
= Unimplemented
Figure 2-2. Control, Status, and Data Registers Summary (Sheet 6 of 8)
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
Freescale Semiconductor
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