MC908MR32CFUE Datasheet, PDF (229/282 Pages) Freescale Semiconductor, Inc – Microcontrollers

I/O Registers
Register Name and Address:
Bit 7
6
Read: CH0F
Write: 0
CH0IE
Reset: 0
0
TASC0 — $0013
5
4
MS0B MS0A
0
0
3
ELS0B
0
2
ELS0A
0
1
TOV0
0
Bit 0
CH0MAX
0
Register Name and Address:
Bit 7
6
Read: CH1F
Write: 0
CH1IE
Reset: 0
0
TASC1 — $0016
5
4
0
MS1A
R
0
0
3
ELS1B
0
2
ELS1A
0
1
TOV1
0
Bit 0
CH1MAX
0
Register Name and Address:
Bit 7
6
Read: CH2F
Write: 0
CH2IE
Reset: 0
0
TASC2 — $0019
5
4
MS2B MS2A
0
0
3
ELS2B
0
2
ELS2A
0
1
TOV2
0
Bit 0
CH2MAX
0
Register Name and Address:
TASC3 — $001C
Bit 7
6
5
4
Read: CH3F
0
CH3IE
MS3A
Write: 0
R
Reset: 0
0
0
0
R
= Reserved
3
ELS3B
0
2
ELS3A
0
Figure 16-8. TIMA Channel Status
and Control Registers (TASC0–TASC3)
1
TOV3
0
Bit 0
CH3MAX
0
CHxF — Channel x Flag Bit
When channel x is an input capture channel, this read/write bit is set when an active edge occurs on
the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the
TIMA counter registers matches the value in the TIMA channel x registers.
When CHxIE = 1, clear CHxF by reading TIMA channel x status and control register with CHxF set,
and then writing a 0 to CHxF. If another interrupt request occurs before the clearing sequence is
complete, then writing 0 to CHxF has no effect. Therefore, an interrupt request cannot be lost due to
inadvertent clearing of CHxF.
Reset clears the CHxF bit. Writing a 1 to CHxF has no effect.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
CHxIE — Channel x Interrupt Enable Bit
This read/write bit enables TIMA CPU interrupts on channel x.
Reset clears the CHxIE bit.
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
Freescale Semiconductor
229