MC908MR32CFUE Datasheet, PDF (219/282 Pages) Freescale Semiconductor, Inc – Microcontrollers

Functional Description
Addr.
$001A
$001B
$001C
$001D
$001E
Register Name
Bit 7
6
5
TIMA Channel 2 Register High ^Read: _{Bit 15}
14
13
(TACH2H) Write:
See page 232. _Reset:
TIMA Channel 2 Register Low ^Read: _{Bit 7}
6
5
(TACH2L) Write:
See page 232. _Reset:
TIMA Channel 3 Status/Control ^{Read: CH3F} _CH3IE
0
Register (TASC3) Write: 0
R
See page 229. _{Reset: 0}
0
0
TIMA Channel 3 Register High ^Read: _{Bit 15}
14
13
(TACH3H) Write:
See page 232. _Reset:
TIMA Channel 3 Register Low ^Read: _{Bit 7}
6
5
(TACH3L) Write:
See page 232. _Reset:
R = Reserved
4
3
2
12
11
10
Indeterminate after reset
4
3
2
Indeterminate after reset
MS3A
ELS3B ELS3A
0
0
0
12
11
10
Indeterminate after reset
4
3
2
Indeterminate after reset
Figure 16-3. TIM I/O Register Summary (Continued)
1
Bit 0
9
Bit 8
1
Bit 0
TOV3 CH3MAX
0
0
9
Bit 8
1
Bit 0
16.3 Functional Description
Figure 16-2 shows the TIMA structure. The central component of the TIMA is the 16-bit TIMA counter that
can operate as a free-running counter or a modulo up-counter. The TIMA counter provides the timing
reference for the input capture and output compare functions. The TIMA counter modulo registers,
TAMODH–TAMODL, control the modulo value of the TIMA counter. Software can read the TIMA counter
value at any time without affecting the counting sequence.
The four TIMA channels are programmable independently as input capture or output compare channels.
16.3.1 TIMA Counter Prescaler
The TIMA clock source can be one of the seven prescaler outputs or the TIMA clock pin, PTE3/TCLKA.
The prescaler generates seven clock rates from the internal bus clock. The prescaler select bits, PS[2:0],
in the TIMA status and control register select the TIMA clock source.
16.3.2 Input Capture
An input capture function has three basic parts:
1. Edge select logic
2. Input capture latch
3. 16-bit counter
Two 8-bit registers, which make up the 16-bit input capture register, are used to latch the value of the
free-running counter after the corresponding input capture edge detector senses a defined transition. The
polarity of the active edge is programmable. The level transition which triggers the counter transfer is
defined by the corresponding input edge bits (ELSxB and ELSxA in TASC0–TASC3 control registers with
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
Freescale Semiconductor
219