33937 Datasheet, PDF (32/47 Pages) Freescale Semiconductor, Inc – Three Phase Field Effect Transistor Pre-driver

FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
LOGIC COMMANDS AND REGISTERS
COMMAND DESCRIPTIONS
The IC contains internal registers to control the various
operating parameters, modes, and interrupt characteristics.
These commands are sent and status is read via 8-bit SPI
commands. The IC will use the last eight bits in an SPI
transfer, so devices can be daisy-chained. The first three bits
in an SPI word can be considered to be the Command with
the trailing five bits being the data.
The SPI logic will generate a framing error and ignore the
SPI message if the number of received bits is not eight or if it
is not a multiple of eight.
After RST, the first SPI result returned is Status Register 0.
Table 7. Command List
Command
Name
000x xxxx
NULL
0010 xxxx
MASK0
0011 xxxx
MASK1
010x xxxx
MODE
0110 xxxx
CLINT0
0111 xxxx
CLINT1
100x xxxx
DEADTIME
Description
These commands are used to read IC status. These commands do not change any internal IC status. Returns
Status Register 0-3, depending on sub command.
Sets a portion of the interrupt mask using lower four bits of command. A “1” bit enables interrupt generation
for that flag. INT remains asserted if uncleared faults are still present. Returns Status Register 0.
Sets a portion of the interrupt mask using lower four bits of command. A “1” bit enables interrupt generation
for that flag. INT remains asserted if uncleared faults are still present. Returns Status Register 0.
Enables Desat/Phase Error Mode. Enables FULLON Mode. Locks further Mode changes. Returns Status
Register 0.
Clears a portion of the fault latch corresponding to MASK0 using lower four bits of command. A 1 bit clears
the interrupt latch for that flag. INT remains asserted if other unmasked faults are still present. Returns Status
Register 0.
Clears a portion of the fault latch corresponding to MASK1 using lower four bits of command. A 1 bit clears
the interrupt latch for that flag. INT remains asserted if other unmasked faults are still present. Returns Status
Register 0.
Set deadtime with calibration technique. Returns Status Register 0.
FAULT REPORTING AND INTERRUPT
GENERATION
Different fault conditions described in the previous
chapters can generate an interrupt - INT pin output signal
asserted high. When an interrupt occurs, the source can be
read from Status Register 0, which is also the return word of
most SPI messages.
Faults are latched on occurrence, and the interrupt and
faults are only cleared by sending the corresponding CLINTx
command. A fault that still exists will continue to assert an
interrupt.
Note: If there are multiple pending interrupts, the INT line
will not toggle when one of the faults is cleared. Interrupt
processing circuitry on the host must be level sensitive to
correctly detect multiple simultaneous interrupt.
Thus, when an interrupt occurs, the host can query the IC
by sending a NULL command; the return word contains flags
indicating any faults not cleared since the CLINTx command
was last written (rising edge of CS) and the beginning of the
current SPI command (falling edge of CS). The NULL
command causes no changes to the state of any of the fault
or mask bits.
The logic clearing the fault latches occurs only when:
1. A valid command had been received(i.e. no framing
error);
2. A state change did not occur during the SPI message
(if the bit is being returned as a 0 and a fault change
occurs during the middle of the SPI message, the latch
will remain set). The latch is cleared on the trailing
(rising) edge of the CS pulse. Note, to prevent missing
any faults the CLINTx command should not generally
clear any faults without being observed; i.e. it should
only clear faults returned in the prior NULL response.
33937
32
Analog Integrated Circuit Device Data
Freescale Semiconductor