33937 Datasheet, PDF (13/47 Pages) Freescale Semiconductor, Inc – Three Phase Field Effect Transistor Pre-driver

ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 8.0 V ≤ V_PWR = V_SUP ≤ 40 V, -40°C ≤ T_A ≤ 135°C, unless otherwise noted. Typical
values noted reflect the approximate parameter means at T_A = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
INTERNAL REGULATORS
V_DD Power-Up Time (Until INT High)
8.0 V ≤ V_PWR ⁽³⁶⁾
VLS Power-Up Time
16 V ≤ V_PWR ⁽³⁷⁾
t_{PU_VDD}
–
t_{PU_VDD}
–
ms
–
2.0
ms
–
2.0
CHARGE PUMP
Charge Pump Oscillator Frequency
Charge Pump Slew Rate⁽³⁸⁾
F_OSC
90
125
190
kHz
SR_CP
–
100
–
V/µs
GATE DRIVE
High Side Turn On Time⁽³⁹⁾
t_ONH
ns
Transition Time from 1.0 to 10 V, Load: C = 500 pF, Rg = 0, (Figure 7)
–
20
35
High Side Turn On Delay⁽⁴⁰⁾
Delay from Command to 1.0 V, (Figure 7)
t_{D_ONH}
ns
130
265
386
High Side Turn Off Time⁽³⁹⁾
t_OFFH
Transition Time from 10 to 1.0 V, Load: C = 500 pF, Rg = 0, (Figure 8)
–
ns
20
35
High Side Turn Off Delay⁽⁴⁰⁾
Delay from Command to 10 V, (Figure 8)
t_{D_OFFH}
ns
130
265
386
Low Side Turn On Time⁽³⁹⁾
t_ONL
ns
Transition Time from 1.0 to 10 V, Load: C = 500 pF, Rg = 0, (Figure 7)
–
20
35
Low Side Turn On Delay⁽⁴⁰⁾
Delay from Command to 1.0 V, (Figure 7)
t_{D_ONL}
ns
130
265
386
Low Side Turn Off Time⁽³⁹⁾
t_OFFL
Transition Time from 10 to 1.0 V, Load: C = 500 pF, Rg = 0, (Figure 8)
–
ns
20
35
Low Side Turn Off Delay⁽⁴⁰⁾
Delay from Command to 10 V, (Figure 8)
t_{D_OFFL}
ns
130
265
386
Same Phase Command Delay Match⁽⁴¹⁾
Thermal Filter Duration ⁽⁴²⁾
t_{D_DIFF}
-20
0
+20
ns
t_DUR
8.0
–
30
µs
Notes
36. The power-up time of the IC depends in part on the time required for this regulator to charge up the external filter capacitor on V_DD.
37. The power-up time of the IC depends in part on the time required for this regulator to charge up the external filter capacitors on VLS and
VLS_CAP. This delay includes the expected time for V_DD to rise.
38. The charge pump operating at 12 V V_SYS, 1.0μF pump capacitor, MUR120 diodes and 47 µF filter capacitor.
39. This parameter is guaranteed by characterization, not production tested.
40. These delays include all logic delays except deadtime. All internal logic is synchronous with the internal clock. The total delay includes
one clock period for state machine decision block, an additional clock period for FULLON mux logic, input synchronization time and
output driver propagation delay. Subtract one clock period for operation in FULLON mode which bypasses the state machine decision
block. Synchronization time accounts for up to one clock period of variation. See Figure 6.
41. The maximum separation or overlap of the High and Low Side gate drives, due to propagation delays when commanding one ON and
the other OFF simultaneously, is guaranteed by design.
42. The output of the overtemperature comparator goes through a digital filter before generating a warning or interrupt.
Analog Integrated Circuit Device Data
Freescale Semiconductor
33937
13