33937 Datasheet, PDF (16/47 Pages) Freescale Semiconductor, Inc – Three Phase Field Effect Transistor Pre-driver

ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 8.0 V ≤ V_PWR = V_SUP ≤ 40 V, -40°C ≤ T_A ≤ 135°C, unless otherwise noted. Typical
values noted reflect the approximate parameter means at T_A = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
SPI INTERFACE TIMING
Maximum Frequency of SPI Operation
f_OP
–
4.0
MHz
Internal Time Base
Internal Time Base drift from value at 25°C ⁽⁵⁰⁾
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) ⁽⁵⁰⁾
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) ⁽⁵⁰⁾
SI to Falling Edge of SCLK (Required Setup Time) ⁽⁵⁰⁾
Falling Edge of SCLK to SI (Required Setup Time) ⁽⁵⁰⁾
SI, CS, SCLK Signal Rise Time ^{(50), (51)}
SI, CS, SCLK Signal Fall Time ^{(50), (51)}
Time from Falling Edge of CS to SO Low-impedance ^{(50), (52)}
Time from Rising Edge of CS to SO High-impedance ^{(50), (53)}
Time from Rising Edge of SCLK to SO Data Valid ^{(50), (54)}
Time from Rising Edge of CS to Falling Edge of the next CS ⁽⁵⁰⁾
f_TB
13
17
25
MHz
TC_TB
-5.0
–
5.0
%
t_LEAD
100
–
–
ns
t_LAG
100
–
–
ns
t_SISU
25
–
–
ns
t_SIHOLD
25
–
–
ns
t_RSI
–
5.0
–
ns
t_FSI
–
5.0
–
ns
t_SOEN
–
55
100
ns
t_SODIS
–
100
125
ns
t_VALID
–
80
125
ns
t_DT
200
–
–
ns
Notes
50. This parameter is guaranteed by design, not production tested.
51. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
52. Time required for valid output status data to be available on SO pin.
53. Time required for output states data to be terminated at SO pin.
54. Time required to obtain valid data out from SO following the rise of SCLK with 200 pF load.
33937
16
Analog Integrated Circuit Device Data
Freescale Semiconductor