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S9S08SG8E2MSC Datasheet, PDF (309/320 Pages) Freescale Semiconductor, Inc – MC9S08SG8 MC9S08SG4 Data Sheet Addendum
Appendix A Electrical Characteristics
A.12 AC Characteristics
This section describes ac timing characteristics for each peripheral system.
A.12.1 Control Timing
Table A-13. Control Timing
Nu
m
C
Rating
Temp
Rated2
Symbol
Min
Typ1
Max
Unit
Sta
ndar
d
AE
C
Gra
de 0
Bus frequency (tcyc = 1/fBus)
1D
–40 C to 125 C
fBus
>125 C
20
x
dc
—
MHz
18
x
Internal low power oscillator period
2D
–40 C to 125 C
tLPO
800
>125 C
600
1500
x
s
1500
x
3 D External reset pulse width3
textrst
100
—
ns
x
x
4 D Reset low drive4
trstdrv
66 x tcyc
—
ns
x
x
Pin interrupt pulse width
8 D Asynchronous path2
Synchronous path5
tILIH, tIHIL
100
1.5 x tcyc
—
—
ns
x
x
Port rise and fall time —
Low output drive (PTxDS = 0) (load = 50 pF)5
Slew rate control disabled (PTxSE = 0)
tRise, tFall
—
Slew rate control enabled (PTxSE = 1)
—
9C
Port rise and fall time —
High output drive (PTxDS = 1) (load = 50 pF)6
Slew rate control disabled (PTxSE = 0)
tRise, tFall
—
Slew rate control enabled (PTxSE = 1)
—
40
—
ns
x
x
75
—
11
—
ns
x
x
35
—
1 Typical values are based on characterization data at VDD = 5.0V, 25C unless otherwise stated.
2 Electrical characteristics only apply to the temperature rated devices marked with x.
3 This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to
override reset requests from internal sources.
4 When any reset is initiated, internal circuitry drives the reset pin low for about 66 cycles of tcyc. After POR reset the bus clock
frequency changes to the untrimmed DCO frequency (freset = (fdco_ut)/4) because TRIM is reset to 0x80 and FTRIM is reset to
0, and there is an extra divide-by-two because BDIV is reset to 0:1. After other resets trim stays at the pre-reset value.
5 Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40C to 125C.
MC9S08SG8 MCU Series Data Sheet, Rev. 7
Freescale Semiconductor
305