PXS20PB Datasheet, PDF (3/30 Pages) Freescale Semiconductor, Inc – 32-bit Power Architecture® Microcontrollers for Highly Reliable

Features
2.1 PXS20 Features
Table 1 displays the PXS20 feature set.
Table 1. PXS20 Family Feature Set
CPU
Buses
Crossbar
Memory
Modules
Type
Feature
Architecture
Execution speed
DMIPS intrinsic performance
SIMD (DSP + FPU)
MMU
Instruction set PPC
Instruction set VLE
Instruction cache
MPU-16 regions
Semaphore unit (SEMA4)
Core bus
Internal periphery bus
Master × slave ports
Code/data flash
Static RAM (SRAM)
Interrupt controller (INTC)
Periodic Interrupt Timer (PIT)
System timer module (STM)
Software watchdog timer (SWT)
eDMA
FlexRay
CAN
UART with DMA support
Clock out
Fault control & collection unit (FCCU)
Cross triggering unit (CTU)
eTimer
PWM
Analog-to-digital converter (ADC)
PXS20
2 × e200z4
(in lock-step or decoupled operation)
Harvard
0 – 120 MHz (+2% FM)
> 240 MIPS
Yes
16 entry
Yes
Yes
4 KB, EDC
Yes, replicated module
Yes
AHB, 32-bit address, 64-bit data
32-bit address, 32-bit data
Lock Step Mode: 4 × 3
Decoupled Parallel Mode: 6 × 3
1 MB, ECC, RWW
128 KB, ECC
16 interrupt levels, replicated module
1 × 4 channels
1 × 4 channels, replicated module
Yes, replicated module
16 channels, replicated module
1 × 64 message buffers, dual channel
2 × 32 message buffers
2
Yes
Yes
Yes
3 × 6 channels
2 Module 4 × (2 + 1) channels
2 × 12-bit ADC, 16 channels per ADC
(3 internal, 4 shared and 9 external)
PXS20 Product Brief, Rev. 1
Freescale Semiconductor
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