PXS20PB Datasheet, PDF (13/30 Pages) Freescale Semiconductor, Inc – 32-bit Power Architecture® Microcontrollers for Highly Reliable

The main features of the SRAMC provide connectivity for the following interfaces:
• XBAR Slave Port (64-bit data path)
• ECSM (ECC Error Reporting, error injection and configuration)
• SRAM array
The following functions are implemented:
• ECC encoding (32-bit boundary for data and complete address bus)
• ECC decoding (32-bit boundary and entire address)
• Address translation from the AHB protocol on the XBAR to the SRAM array
The platform SRAM controller is replicated for each processor.
Features
2.5.9 Memory Subsystem Access Time
Every memory access the CPU performs requires at least one system clock cycle for the data phase of the
access. Slower memories or peripherals may require additional data phase wait states. Additional data
phase wait states may also occur if the slave being accessed is not parked on the requesting master in the
crossbar.
Table 2 shows the number of additional data phase wait states required for a range of memory accesses.
Table 2. Platform Memory Access Time Summary
AHB transfer
e200z4d instruction fetch
e200z4d instruction fetch
e200z4d data read
e200z4d data write
e200z4d data write
e200z4d data write
e200z4d flash memory read
e200z4d flash memory read
Data phase
wait states
Description
0
Flash memory prefetch buffer hit (page hit)
3
Flash memory prefetch buffer miss
(based on 4-cycle random flash array access time)
0–1
SRAM read
0
SRAM 32-bit write
0
SRAM 64-bit write (executed as 2 x 32-bit writes)
0–2
SRAM 8-,16-bit write
(Read-modify-Write for ECC)
0
Flash memory prefetch buffer hit (page hit)
3
Flash memory prefetch buffer miss (at 120 MHz; includes 1 cycle
of program flash memory controller arbitration)
2.5.10 Error Correction Status Module (ECSM)
The ECSM on this device manages the ECC configuration and reporting for the platform memories (flash
memory and SRAM). It does not implement the actual ECC calculation. A detected error (double error for
flash memory or SRAM) is also reported to the FCCU. The following errors and indications are reported
into the ECSM dedicated registers:
• ECC error status and configuration for flash memory and SRAM
• ECC error reporting for flash memory
PXS20 Product Brief, Rev. 1
Freescale Semiconductor
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