PXS20PB Datasheet, PDF (22/30 Pages) Freescale Semiconductor, Inc – 32-bit Power Architecture® Microcontrollers for Highly Reliable

Features
• Independent control of both edges of each PWM output
• Synchronization to external hardware or other PWM supported
• Double buffered PWM registers
— Integral reload rates from 1 to 16
— Half cycle reload capability
• Multiple ADC trigger events can be generated per PWM cycle via hardware
• Fault inputs can be assigned to control multiple PWM outputs
• Programmable filters for fault inputs
• Independently programmable PWM output polarity
• Independent top and bottom deadtime insertion
• Each complementary pair can operate with its own PWM frequency and deadtime values
• Individual software control for each PWM output
• All outputs can be forced to a value simultaneously
• PWMX pin can optionally output a third signal from each channel
• Channels not used for PWM generation can be used for buffered output compare functions
• Channels not used for PWM generation can be used for input capture functions
• Enhanced dual edge capture functionality
• Option to supply the source for each complementary PWM signal pair from any of the following:
— External digital pin
— Internal timer channel
— External ADC input, taking into account values set in ADC high- and low-limit registers
• DMA support
2.5.31 eTimer Module
The PXS20 provides three eTimer modules on the 257 MAPBGA device, and two eTimer modules on the
144 LQFP package. Six 16-bit general purpose up/down timer/counters per module are implemented with
the following features:
• Maximum clock frequency of 120 MHz
• Individual channel capability
— Input capture trigger
— Output compare
— Double buffer (to capture rising edge and falling edge)
— Separate prescaler for each counter
— Selectable clock source
— 0–100% pulse measurement
— Rotation direction flag (Quad decoder mode)
• Maximum count rate
PXS20 Product Brief, Rev. 1
22
Freescale Semiconductor