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S9S12C128F0MFUE Datasheet, PDF (299/690 Pages) Freescale Semiconductor, Inc – Reference Manual | |||
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Chapter 10 Freescaleâs Scalable Controller Area Network (S12MSCANV2)
Table 10-8. Time Segment 1 Values
TSEG13
TSEG12
TSEG11
TSEG10
Time segment 1
0
0
0
0
1 Tq clock cycle(1)
0
0
0
1
2 Tq clock cycles1
0
0
1
0
3 Tq clock cycles1
0
0
1
1
4 Tq clock cycles
:
:
:
:
:
1
1
1
0
15 Tq clock cycles
1
1
1
1
16 Tq clock cycles
1. This setting is not valid. Please refer to Table 10-34 for valid settings.
The bit time is determined by the oscillator frequency, the baud rate prescaler, and the number of time
quanta (Tq) clock cycles per bit (as shown in Table 10-7 and Table 10-8).
Eqn. 10-1
Bit Time= (---P----r---e---f-s-C--c---A-a----Nl--e--C-r----L--v--K-a----l--u----e----) ⢠(1 + TimeSegment1 + TimeSegment2)
10.3.2.5 MSCAN Receiver Flag Register (CANRFLG)
A ï¬ag can be cleared only by software (writing a 1 to the corresponding bit position) when the condition
which caused the setting is no longer valid. Every ï¬ag has an associated interrupt enable bit in the
CANRIER register.
Module Base + 0x0004
7
R
WUPIF
W
6
CSCIF
5
RSTAT1
4
RSTAT0
3
TSTAT1
2
TSTAT0
1
OVRIF
0
RXF
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 10-8. MSCAN Receiver Flag Register (CANRFLG)
NOTE
The CANRFLG register is held in the reset state1 when the initialization
mode is active (INITRQ = 1 and INITAK = 1). This register is writable again
as soon as the initialization mode is exited (INITRQ = 0 and INITAK = 0).
Read: Anytime
Write: Anytime when out of initialization mode, except RSTAT[1:0] and TSTAT[1:0] ï¬ags which are read-
only; write of 1 clears ï¬ag; write of 0 is ignored.
1. The RSTAT[1:0], TSTAT[1:0] bits are not affected by initialization mode.
Freescale Semiconductor
MC9S12C-Family / MC9S12GC-Family
299
Rev 01.24
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