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S9S12C128F0MFUE Datasheet, PDF (292/690 Pages) Freescale Semiconductor, Inc – Reference Manual | |||
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Chapter 10 Freescaleâs Scalable Controller Area Network (S12MSCANV2)
Register
Name
Bit 7
6
5
4
3
2
1
0x0010â0x0013 R
CANIDAR0â3 W AC7
AC6
AC5
AC4
AC3
AC2
AC1
0x0014â0x0017 R
CANIDMRx
W
AM7
0x0018â0x001B R
CANIDAR4â7 W AC7
0x001Câ0x001F R
CANIDMR4â7 W
AM7
AM6
AC6
AM6
AM5
AC5
AM5
AM4
AC4
AM4
AM3
AC3
AM3
AM2
AC2
AM2
AM1
AC1
AM1
0x0020â0x002F R
CANRXFG
W
0x0030â0x003F R
CANTXFG
W
See Section 10.3.3, âProgrammerâs Model of Message Storageâ
See Section 10.3.3, âProgrammerâs Model of Message Storageâ
= Unimplemented or Reserved
u = Unaffected
Figure 10-3. MSCAN Register Summary (continued)
Bit 0
AC0
AM0
AC0
AM0
10.3.2 Register Descriptions
This section describes in detail all the registers and register bits in the MSCAN module. Each description
includes a standard register diagram with an associated ï¬gure number. Details of register bit and ï¬eld
function follow the register diagrams, in bit order. All bits of all registers in this module are completely
synchronous to internal clocks during a register read.
10.3.2.1 MSCAN Control Register 0 (CANCTL0)
The CANCTL0 register provides various control bits of the MSCAN module as described below.
Module Base + 0x0000
R
W
Reset:
7
RXFRM
0
6
RXACT
5
CSWAI
4
SYNCH
3
TIME
2
WUPE
0
0
0
0
0
= Unimplemented
Figure 10-4. MSCAN Control Register 0 (CANCTL0)
1
SLPRQ
0
0
INITRQ
1
292
MC9S12C-Family / MC9S12GC-Family
Freescale Semiconductor
Rev 01.24
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