33970 Datasheet, PDF (27/36 Pages) Freescale Semiconductor, Inc – Dual Gauge Driver Integrated Circuit with Improved Damping Algorithms

FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
percent due to process variation. Using the existing SPI
inputs and the precision timing reference already available to
the microcontroller, the 33970 allows clock calibration to
within ±10 percent.
Calibrating the internal 1.0 MHz clock is initiated by writing
a logic [1] to PECCR bit PE3 (see Figure 10, page 27). The
8.0 µs calibration pulse that is then provided by the controller
will ideally result in an internal 33970 clock speed of 1.0 MHz.
The pulse is sent on the CS pin immediately after the SPI
word is sent. No other SPI lines should be toggled. At the
moment the CS pin transitions from logic [1] to logic [0], an
internal 7-bit counter counts the number of cycles of an
internal 8.0 MHz clock. The counter stops when the CS pin
transitions from logic [0] to logic [1]. The value in the counter
represents the number of cycles of the 8.0 MHz clock
occurring in the 8.0 µs window; it should range from 32 to
119. An offset is added to this number to help center or skew
the calibrated result to generate a desired maximum or
nominal frequency. The modified counter value is truncated
by 4 bits to generate the calibration divisor, which should
range from 4 to 15. The 8.0 MHz clock is divided by the
calibration divisor, resulting in a calibrated 1.0 MHz clock. If
the calibration divisor lies outside the range of 4 to 15, the
33970 flags the CAL bit of the status bits, indicating the
calibration procedure was not successful. A clock calibration
is allowed only if the gauges are disabled or the pointers are
not moving, as indicated by status bits MOV1 and MOV0.
D15
SI
SCLK
CS
PECCR Command
D0
8.0 µs Calibration Pulse
Figure 10. Gauge Enable and Clock Calibration Example
Some applications may require a guaranteed maximum
pointer velocity and acceleration. Guaranteeing these
maximums requires nominal internal clock frequency falls
below 1.0 MHz. The frequency range of the calibrated clock
will always be below 1.0 MHz if PECCR bit PE4 is logic [0]
prior to initiating a calibration command, followed by an
8.0 µs reference pulse. The frequency will be centered at
1.0 MHz if bit D4 is logic [1].
The 33970 can be fooled into calibrating faster or slower
than the optimal frequency by sending a calibration pulse
longer or shorter than the intended 8.0 µs. As long as the
count remains between 4 and 15, there will be no clock
calibration flag. For applications requiring a slower calibrated
clock — e.g., a motor designed with a gear ratio of 120:1
(8 microsteps/deg) — the user will have to provide a longer
calibration pulse. The device allows a SPI-selectable slowing
of the internal oscillator, using the PECCR command, so that
the calibration divisor safely falls within the 4-to-15 range
when calibrating with a longer time reference. For example,
for the 120:1 motor, the pulse would be 12 µs instead of
8.0 µs. The result of this slower calibration results in the
longer step times necessary to generate pointer movements
meeting acceleration and velocity requirements. The
resolution of the pointer positioning decreases from
0.083 deg/microstep (180:1) to 0.125 deg/microstep (120:1).
The pointer sweep range increases from approximately
340 degrees to over 500 degrees.
Note Be aware that a fast calibration could result in
violations of the motor acceleration and velocity maximums,
resulting in missed steps.
POINTER DECELERATION
Constant acceleration and deceleration of the pointer
produces relatively choppy movements when compared to
those of an air core gauge. Air core behavior can be
simulated with appropriate ramp modification during
deceleration. This shaping can be accomplished by adding
repetitive steps at several of the last step values as the
pointer decelerates. The default movement in the 33970 uses
this ramp modification feature. An example is shown in
Figure 11. If the maximum acceleration and deceleration of
the pointer is desired, the repetitive steps can be disabled by
writing logic [1] to the PECCR bit PE5.
Analog Integrated Circuit Device Data
Freescale Semiconductor
33970
27