33970 Datasheet, PDF (14/36 Pages) Freescale Semiconductor, Inc – Dual Gauge Driver Integrated Circuit with Improved Damping Algorithms

FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
it is failing or is not being used. The device can be placed into
a standby current mode by writing a logic [0] to both PE0 and
PE1. During this state, most current consuming circuits are
biased off. When in the Standby mode, the internal clock will
remain ON.
The internal state machine utilizes a ROM table of step
times defining the duration that the motor will spend at each
microstep as it accelerates or decelerates to a commanded
position. The accuracy of the acceleration and velocity of the
motor is directly related to the accuracy of the internal clock.
Although the accuracy of the internal clock is temperature
independent, the non-calibrated tolerance is +70% to -35%.
The 33970 was designed with a feature allowing the internal
clock to be software calibrated to a tighter tolerance of ±10%,
using the CS pin and a reference time pulse provided by the
microcontroller.
Calibration of the internal clock is initiated by writing a
logic [1] to PE3. The calibration pulse, which must be 8.0 µs
for an internal clock speed of 1.0 MHz, will be sent on the CS
pin immediately after the SPI word is sent. No other SPI lines
will be toggled. A clock calibration will be allowed only if the
gauges are disabled or the pointers are not moving, as
indicated by status bits MOV0 and MOV1. Additional details
are provided in the INTERNAL CLOCK CALIBRATION
section, beginning on page 26.
Some applications may require a guaranteed maximum
pointer velocity and acceleration. Guaranteeing these
maximums requires that the nominal internal clock frequency
fall below 1.0 MHz. The frequency range of the calibrated
clock will always be below 1.0 MHz if bit PE4 is logic [0] when
initiating a calibration command, followed by an 8.0 µs
reference pulse. The frequency will be centered at 1.0 MHz if
bit PE4 is logic [1].
Some applications may require a slower calibrated clock
due to a lower motor gear reduction ratio. Writing a logic [1]
to bit PE2 will slow the internal oscillator by one-third. Slowing
the clock accommodates a longer calibration pulse without
overrunning the internal counter—a condition designed to
generate a CAL fault indication. For example, calibration for
a clock frequency of 667 kHz would require a calibration
pulse of 12 µs. Unless the internal oscillator is slowed by
writing PE2 to logic [1], a 12 µs calibration pulse may overrun
the counter and generate a CAL fault indication.
Some applications may require faster pointer positioning
than is provided with the air core motor emulation feature.
This feature is enabled with the device that is in the default
mode. Writing logic [1] to bit PE5 will disable the air core
emulation and provide a constant acceleration and
deceleration at the maximum rate.
Bit D6 is logic [0] during a PECCR commands.
The default Pointer Position 0 (PE7 = 0) will be the farthest
counter-clockwise position. A logic [1] written to bit PE7 will
change the location of the position 0, for the Gauge selected
by bit PE8, to the farthest clockwise position. A change in
position 0 of only one, or both, of the two coils can be
accomplished by using bits PE8 and PE7. Performing an RTZ
will always move the pointer to position 0. Exercise care
when writing to PECCR bits PE8 and PE7 in order to prevent
accidental changes of the position 0 locations.
Bits PE11:PE8 determine the content of the bits clocked
out of the SO pin. When bit PE11 is at logic [0], the clocked
out bits will provide device status. If a logic [1] is written to bit
PE11, the bits clocked out of the SO pin, depending upon the
state of bits PE10:PE8, provides either:
• Accumulator information and detection status during
the RTZ (PE10 logic [0])
• Real time pointer position location at the time CS goes
low (PE10 logic [1] and PE9 logic [0]), or
• The real time step position of the pointer as described
in the velocity Table 21, page 24 (PE10, PE9, and PE8
logic [1]).
Additional details are provided in the SO Communication
section beginning on page 18.
If bit PE12 is logic [1] during a PECCR command, the state
of PE11:PE0 is ignored. This is referred to as the null
command and can be used to read device status without
affecting device operation.
Table 7. Power, Enable, Calibration, and Configuration Register (PECCR)
Address 000
Bits D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Read –
–
–
–
–
–
–
–
–
–
–
–
–
Write PE12 PE11 PE10 PE9
PE8
PE7
0
PE5
PE4
PE3
PE2
PE1
PE0
The bits in Table 7 are write-only.
PE12 (D12) — Null Command for Status Read
• 0 = Disable
• 1 = Enable
PE11 (D11) — Status Select bit. This bit selects the
information clocked out of the SO pin.
• 0 = Device Status (the logic states of PE10, PE9, and
PE8 don’t cares)
• 1 = RTZ Accumulator Value, Gauge 0 or 1 Pointer
position, or Gauge 0 and 1 Velocity ramp position
(depending upon the logic states of PE10, PE9, and
PE8)
PE10 (D10) — RTZ Accumulator or Pointer Status Select
bit. This bit is recognized only when PE11 = 1.
• 0 = RTZ Accumulator Value and status
• 1 = Pointer Position or Speed
33970
14
Analog Integrated Circuit Device Data
Freescale Semiconductor