33970 Datasheet, PDF (10/36 Pages) Freescale Semiconductor, Inc – Dual Gauge Driver Integrated Circuit with Improved Damping Algorithms

FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
This 33970 is a single-packaged, Serial Peripheral
Interface (SPI) controlled, dual step motor gauge driver
integrated circuit (IC). This monolithic IC consists of four dual
output H-Bridge coil drivers and the associated control logic.
Each pair of H-Bridge drivers is used to automatically control
the speed, direction, and magnitude of current through the
two coils of a two-phase instrumentation step motor, similar
to an MMT-licensed AFIC 6405.
The 33970 is ideal for use in automotive instrumentation
systems requiring distributed and flexible step motor gauge
driving. The device also eases the transition to step motors
from air core motors by emulating the air core pointer
movement with little additional processor bandwidth
utilization.
FUNCTIONAL PIN DESCRIPTION
H-Bridge Outputs 0 (COS0+, COS0-, SIN0+, SIN0-)
Each pin is the output pin of a half bridge, designed to
source or sink current. The H-Bridge pins linearly drive the
sine and cosine coils of two separate step motors to provide
four-quadrant operation.
GROUND (GND)
These pins serve as the ground for the source of the low-
side output transistors as well as the logic portion of the
device. They also help dissipate heat from the device.
CHIP SELECT (CS)
The CS pin enables communication with the master
device. When this pin is in a logic [0] state, the 33970 is
capable of transferring information to, and receiving
information from, the master. The 33970 latches data in from
the Input Shift registers to the addressed registers on the
rising edge of CS. The output driver on the SO pin is enabled
when CS is logic [0]. When CS is logic high, signals at the
SCLK and SI pins are ignored and the SO pin is tri-stated
(high impedance). CS will only be transitioned from a logic [1]
state to a logic [0] state when SCLK is a logic [0]. CS has an
internal pull-up (l_UP) connected to the pin, as specified in the
section of the Static Electrical Characteristics table entitled
CONTROL I/O, which is found on page 6.
SERIAL CLOCK (SCLK)
SCLK clocks the Internal Shift registers of the 33970
device. The Serial Input (SI) pin accepts data into the Input
Shift register on the falling edge of the SCLK signal, while the
Serial Output pin (SO) shifts data information out of the SO
Line Driver on the rising edge of the SCLK signal. It is
important that the SCLK pin be in a logic [0] state whenever
the CS makes any transition. SCLK has an internal pull down
(l_DWN), as specified in the section of the Static Electrical
Characteristics table entitled CONTROL I/O, which is found
on page 6. When CS is logic [1], signals at the SCLK and SI
pins are ignored and SO is tri-stated (high impedance). Refer
to the data transfer timing diagrams in Figure 6 and Figure 7
on page 12.
SERIAL OUTPUT (SO)
The SO data pin is a tri-stateable output from the Shift
register. The Status register bits are the first 16 bits shifted
out. Those bits are followed by the message bits clocked in
FIFO, when the device is in a daisy chain connection or being
sent words that are multiples of 16 bits. Data is shifted on the
rising edge of the SCLK signal. The SO pin will remain in a
high impedance state until the CS pin is put into a logic low
state.
SERIAL INPUT (SI)
The SI pin is the input of the Serial Peripheral Interface
(SPI). Serial Input (SI) information is read on the falling edge
of SCLK. A 16-bit stream of serial data is required on the SI
pin, beginning with the most significant bit (MSB). Messages
that are not multiples of 16 bits (e.g., daisy chained device
messages) are ignored. After transmitting a 16-bit word, the
CS pin must be de-asserted (logic [1]) before transmitting a
new word. SI information is ignored when CS is in a logic high
state.
Multiplexed Output (RTZ)
This is a multiplexed output pin, for the non-driven coil,
during a Return to Zero (RTZ) event.
Voltage (VDD)
This SPI and logic power supply input will work with 5.0 V
supplies.
RESET (RST)
If the master decides to reset the device, or place it into a
sleep state, the RST pin is driven to a logic [0]. A logic [0] on
the RST pin will force all internal logic to the known default
state. This input has an internal active pull-up.
BATTERY VOLTAGE (VPWR)
Power supply.
33970
10
Analog Integrated Circuit Device Data
Freescale Semiconductor