MC9S08QE8 Datasheet, PDF (19/46 Pages) Freescale Semiconductor, Inc – 8-Bit HCS08 Central Processor Unit

Electrical Characteristics
3.10.1 Control Timing
Table 11. Control Timing
Num C
Rating
Symbol
Min
Typical¹ Max Unit
1
D Bus frequency (t_cyc = 1/f_Bus)
f_Bus
dc
—
10
MHz
2 D Internal low power oscillator period
t_LPO
700
—
1300 μs
3 D _{External reset pulse width}²
t_extrst
100
—
—
ns
4 D Reset low drive
t_rstdrv
34 x t_cyc
—
—
ns
5
D
BKGD/MS setup time after issuing background debug
force reset to enter user or BDM modes
t_MSSU
500
—
—
ns
6
D
BKGD/MS hold time after issuing background debug
force reset to enter user or BDM modes ³
t_MSH
100
—
—
μs
IRQ pulse width
7
D Asynchronous path²
Synchronous path⁴
t_ILIH, t_IHIL
100
—
1.5 × t_cyc
—
—
ns
—
8 D Keyboard interrupt pulse width
Asynchronous path²
Synchronous path⁴
t_ILIH, t_IHIL
100
—
1.5 × t_cyc
—
—
ns
—
Port rise and fall time —
Low output drive (PTxDS = 0) (load = 50 pF)⁵
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
9
C
Port rise and fall time —
High output drive (PTxDS = 1) (load = 50 pF)⁵
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
t_Rise, t_Fall
—
—
t_Rise, t_Fall
—
—
16
—
ns
23
—
5
—
ns
9
—
1 _{Typical values are based on characterization data at VDD = 3.0V, 25°C unless otherwise stated.}
2 _{This is the shortest pulse that is guaranteed to be recognized as a reset pin request.}
3 _{To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of tMSH after VDD}
rises above V_LVD.
4 _{This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or}
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized.
5 _{Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40°C to 85°C.}
RESET PIN
t_extrst
Figure 14. Reset Timing
MC9S08QE8 Series, Rev. 3
Freescale Semiconductor
Preliminary
19
Subject to Change Without Notice