MC33999 Datasheet, PDF (16/21 Pages) Motorola, Inc – 16-Output Switch with SPI and PWM Control

FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
PWM ENABLE REGISTER
The PWM Enable register determines the outputs that are
PWM controlled. The first 8 bits of the 24 bit SPI message
word are used to identify the PWM enable command, and the
remaining 16 bits are used to enable or disable the PWM of
the output drivers.
A logic [1] in the PWM Enable register allows the user to
OR / AND the PWM input with SPI Control bit and disables the
specific parallel control input (PWM0, PWM1, PWM6, PWM7,
PWM8, PWM9, PWM14, and PWM15).
A logic [0] in the PWM Enable register will disable the
PWM to a specific output and allow the user to use the
parallel PWM control inputs (PWM0, PWM1, PWM6, PWM7,
PWM8, PWM9, PWM14, and PWM15) and the SPI ON /OFF
Control bits. Power-ON Reset (POR) or the RST pin or the
RESET command will set the PWM enable register to
logic[0].
AND /OR Control Register
The AND /OR Control register describes the condition by
which the PWM pin controls the output driver. A logic [0] in
the AND / OR Control register will AND the PWM pin with the
control bit in the SPI Control register. Likewise, a logic [1] in
the AND / OR Control register will OR the PWM pin with the
control bit in the ON/OFF Control register (see Figure 13).
On/Off Control Bit
On/Off Control Bit
PWM Enable Bit
PWM IN
AND/OR Control Bit
To Gate
Control
SERIAL OUTPUT (SO) RESPONSE REGISTER
Fault reporting is accomplished through the SPI interface.
All logic [1]s received by the MCU via the SO pin indicate
fault. All logic [0]s received by the MCU via the SO pin
indicate no fault. All fault bits are cleared on the positive edge
of CS. SO bits 15 to 0 represent the fault status of outputs 15
to 0. SO bits 21 to 16 will always return logic [0]. Bit 22
provides overvoltage condition status, and bit 23 is set when
any fault is present in the IC. The timing between two write
words must be greater than 450 µs to allow adequate time to
sense and report the proper fault status.
RESET COMMAND
The RESET command turns all outputs OFF and sets all
internal registers to their Power-ON Reset state (refer to
Table 5).
FAULT OPERATION
On each SPI communication, a 24-bit command word is
sent to the 33999 and a 24-bit fault word is received from the
33999.
The Most Significant Bit (MSB) is sent and received first.
Command Register Definition:
0 = Output Command Off
1 = Output Command On
SO Definition:
0 = No fault
1 = Fault
On/Off control Bit
PWM IN
Figure 13. PWM Control Logic Diagram
33999
16
Analog Integrated Circuit Device Data
Freescale Semiconductor