33810_11 Datasheet, PDF (13/37 Pages) Freescale Semiconductor, Inc – Automotive Engine Control IC Quad injector driver with Parallel/SPI control

ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions of 3.0 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 32 V, -40°C ≤ TC ≤ 125°C, and calibrated
timers, unless otherwise noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR
= 13 V, TA = 25°C.
Characteristic
GENERAL PURPOSE GATE DRIVER PARAMETERS
Symbol
Min
Typ
Max
Unit
Short to Battery Fault Detection Filter Timer Accuracy
VDD = High, Outputs Programmed ON
Programmable from 30 µs to 960 µs in replicating increments
Tolerance of timer after using calibration command
Tolerance of timer before using calibration command
Output OFF Open Circuit Fault Filter Timer
VDD = 5.0 V, Outputs Off
Tolerance of timer before using calibration command
PWM Frequency 10 Hz to 1.28 kHz Tolerance after using calibration
command
PWM Frequency 10 Hz to 1.28 kHz Tolerance before using calibration
command
V_DS(flt-th)
t_(OFF)OC
PWM_FREQ
PWM_FREQ
-10
-35
100
-10%
-35%
%
+10
+35
µs
400
10%
35%
Gate Driver Short Fault Duty Cycle
SPI DIGITAL INTERFACE TIMING⁽¹⁴⁾
GD_{SHRT_DC}
1.0
3.0
%
Falling Edge of CS to Rising Edge of SCLK
Required Setup Time
Falling Edge of SCLK to Rising Edge of CS
Required Setup Time
SI to Rising Edge of SCLK
Required Setup Time
Rising Edge of SCLK to SI
Required Hold Time
SI, CS, SCLK Signal Rise Time⁽¹⁵⁾
SI, CS, SCLK Signal Fall Time⁽¹⁶⁾
Time from Falling Edge of CS Low-impedance⁽¹⁷⁾
Time from Rising Edge off CS to SO High-impedance⁽¹⁸⁾
Time from Falling Edge of SCLK to SO Data Valid⁽¹⁹⁾
Sequential Transfer Rate
Time required between data transfers
t _LEAD
100
–
t _LAG
50
–
t _{SI (SU)}
16
–
t _{SI (HOLD)}
20
–
t _{R (SI)}
–
5.0
t _{F (SI)}
–
5.0
t _{SO (EN)}
–
–
t _{SO (DIS)}
–
–
t _VALID
–
25
t_STR
1.0
–
ns
–
ns
–
ns
–
ns
–
–
ns
–
ns
55
ns
55
ns
55
ns
–
µs
DIGITAL INTERFACE
Calibrated Timer Accuracy
t _TIMER
–
–
10
%
Un-calibrated Timer Accuracy
t _TIMER
–
–
35
%
Notes
14. These parameters are guaranteed by design. Production test equipment uses 1.0 MHz, 5.0 V SPI interface.
15. This parameter is guaranteed by design, however it is not production tested.
16. Rise and Fall time of incoming SI, CS and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
17. Time required for valid output status data to be available on SO pin.
18. Time required for output states data to be terminated at SO pin.
19. Time required to obtain valid data out from SO following the fall of SCLK with 200 pF load.
Analog Integrated Circuit Device Data
Freescale Semiconductor
33810
13