MC9S12H256 Datasheet, PDF (121/130 Pages) Motorola, Inc – Device User Guide

Freescale Semicondu_Mc_Ct₉o_S1r₂,_HI₂n₅₆c_D._{evice User Guide — V01.18}
A.8 External Bus Timing
A timing diagram of the external multiplexed-bus is illustrated in Figure A-9 with the actual timing values
shown on table Table A-20. All major bus signals are included in the diagram. While both a data write
and data read cycle are shown, only one or the other would occur on a particular bus cycle.
A.8.1 General Muxed Bus Timing
The expanded bus timings are highly dependent on the load conditions. The timing parameters shown
assume a balanced load across all outputs.
For More Information On This Product,
Go to: www.freescale.com