MC9S12H256 Datasheet, PDF (110/130 Pages) Motorola, Inc – Device User Guide

MC9S12H256 Device User Gui^Fde^r—^eeV^s01^c.1^a8 ^{le Semiconductor, Inc.}
The loop bandwidth f_C should be chosen to fulfill the Gardner’s stability criteria by at least a factor of 10,
typical values are 50. ζ = 0.9 ensures a good transient response.
f_C < ----------2-----^â‹---^ζ----^â‹---f--^r--^e----^f---------
π ⋅ _{ζ} + 1 + ζ²_
5--1--0-- ^{→ fC <} 4----f-⋅^{r--e-5---f-0- ;(ζ = 0.9)}
And finally the frequency relationship is defined as
n = -f-^V-f--_r-^C-_e---_fO--- = 2 ⋅ (synr + 1)
With the above inputs the resistance can be calculated as:
R = ^2-----â‹---^π---K--^â‹--_Φ-n-----^â‹---f--^C--
The capacitance C_s can now be calculated as:
C_s = -_π----2_â‹---f--^â‹_C---^ζ--_â‹-²--R--- ≈ ^0-f--_C-.--5--_â‹-1--R-6--;(ζ = 0.9)
The capacitance C_p should be chosen in the range of:
C_s ⁄ 20 ≤ C_p ≤ C_s ⁄ 10
The stabilization delays shown in Table A-15 are dependant on PLL operational settings and external
component selection (e.g. crystal, XFC filter).
A.4.3.2 Jitter Information
The basic functionality of the PLL is shown in Figure A-2. With each transition of the clock f_cmp, the
deviation from the reference clock f_ref is measured and input voltage to the VCO is adjusted
accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency.
Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock
jitter. This jitter affects the real minimum and maximum clock periods as illustrated in Figure A-3.
For More Information On This Product,
Go to: www.freescale.com