MC81F4216 Datasheet, PDF (175/200 Pages) Finechips – ABOV SEMICONDUCTOR 8-BIT SINGLE-CHIP MICROCONTROLLERS

MC81F4x16
Release the STOP mode
The source for exit from STOP mode is hardware reset, external interrupt, Timer, Watch Timer, IIC
Slave, SIO or UART. Reset re-defines all the Control registers but does not change the on-chip
RAM(Be careful, If the code is compiled with RAM clear option, RAM is cleared after reset by ram
clear routine. It is possible to disable the RAM clear option by option menu).
If I-flag = 1, the normal interrupt response takes place. If I-flag = 0, the chip will resume execution
starting with the instruction following the STOP instruction. It will not vector to interrupt service routine.
(refer to Figure 27-3) When exit from Stop mode by external interrupt, enough oscillation stabilization
time is required to normal operation. Figure 27-4 shows the timing diagram. When released from the
Stop mode, the Basic interval timer is activated on wake-up. It is increased from 00H until FFH. The
count overflow is set to start normal operation. Therefore, before STOP instruction, user must be set
its relevant prescaler divide ratio to have long enough time (more than 20msec). This guarantees that
oscillator has started and stabilized. By reset, exit from Stop mode is shown in Figure 27-5.
Figure 27-3 STOP Releasing Flow by Interrupts
October 19, 2009 Ver.1.35
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