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MC81F4216 Datasheet, PDF (152/200 Pages) Finechips – ABOV SEMICONDUCTOR 8-BIT SINGLE-CHIP MICROCONTROLLERS | |||
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MC81F4x16
24.1 Registers
UCONH
UART CONTROL HIGH REGISTER (UCONH)
00FCH
When current mode is 2 or 3, and the âMCEâ bit is enabled, Rx interrupt is generated when only 9th bit
of Rx data is â1â. This feature is used to Multiprocessor Communication. See â24.4 Muti-processor
Communicationâ on page 160 for more detail information.
In mode 1, and the âMCEâ bit is enabled, Rx interrupt is generated when only valid stop bit is received.
In mode 0, the âMCEâ bit must be â0â.
TB8 and RB8 bits are ignored when current mode is 0 or 1, or the âUTP(UCONL.7 / UART parity auto-
generation)â bit is enabled.
7
6
5
4
3
2
1
UCONH UMS1 UMS0 MCE SDR TB8 RB8
â
R/W R/W R/W R/W R/W R/W â
0
â Reset value: 00H
â
UMS
MCE
SDR
TB8
UART Mode Selection Bits
Multiprocessor Communication Enable Bit
(for modes 2 and 3 only)
Serial Data Receive Enable Bit
00: Mode 0; Synchronous mode
(fu/(16Ã(BRDAT+1)))
01: Mode 1; 8-bit UART
(fu/(16Ã(BRDAT+1)))
10: Mode 2; 9-bit UART
(fxx/16)
11: Mode 3; 9-bit UART
(fu/(16Ã(BRDAT+1)))
0: Disable
1: Enable
0: Receive Disable
1: Receive Enable
TB8
9th bit of Tx Data
RB8
RB8
â
bit1 â bit0
9th bit of Rx Data
Not used for MC81F4x16
Note : âfuâ is the clock source which is selected by the UCLK(UCONL.[2-3]) bits.
152
October 19, 2009 Ver.1.35
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