MC81F4216 Datasheet, PDF (173/200 Pages) Finechips – ABOV SEMICONDUCTOR 8-BIT SINGLE-CHIP MICROCONTROLLERS

MC81F4x16
The exit from SLEEP mode is hardware reset or all interrupts. Reset re-defines all the Control
registers but does not change the on-chip RAM (Be careful, If the code is compiled with RAM clear
option, RAM is cleared after reset by ram clear routine. It is possible to disable the RAM clear option
by option menu). Interrupts allow both on-chip RAM and Control registers to retain their values. If I-
flag = 1, the normal interrupt response takes place. If I-flag = 0, the chip will resume execution starting
with the instruction following the SLEEP instruction. It will not vector to interrupt service routine. (refer
to Figure 27-3)
When exit from SLEEP mode by reset, enough oscillation stabilization time is required to normal
operation. Figure 27-2 shows the timing diagram. When released from the SLEEP mode, the Basic
interval timer is activated on wake-up. It is increased from 00H until FFH. The count overflow is set to
start normal operation.
Note :
After SLEEP mode, at least one or more NOP instruction for data bus pre-charge time
should be written.
LDM SSCR,#0FH
NOP
NOP
;for data bus pre-charge time
;for data bus pre-charge time
Figure 27-1 SLEEP Mode Release Timing by External Interrupt
Figure 27-2 Timing of SLEEP Mode Release by Reset
October 19, 2009 Ver.1.35
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