MC81F4216 Datasheet, PDF (125/200 Pages) Finechips – ABOV SEMICONDUCTOR 8-BIT SINGLE-CHIP MICROCONTROLLERS

MC81F4x16
Function Description
Interval Timer Mode
A match signal is generated and T0O pins are toggled when the T0CR+T1CR register value equals
the T0DR+T1DR. The match signal generates a timer match interrupt and clears the T0CR and the
T1CR register.
If, for example, you write the value 24H to T0DR, 10H to T1DR and 9FH to T0SCR, the counter will
increment until it reaches 1024H. At this point, the Timer 0 math interrupt request is generated, the
counter value is reset, and counting resumes.
Pulse Width Modulation Mode
Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output
at the PWM0O pin. As in interval timer mode, a match signal is generated when the counter value is
identical to the value written to the T0DR+T1DR. In PWM mode, however, the match signal does not
clear the counter. Instead, it runs continuously, overflowing at FFH, and then continues incrementing
from 0000H.
Although you can use the match signal to generate a timer 0 overflow interrupt, interrupts are not
typically used in PWM-type applications. Instead, the pulse at the PWM0O pin is held to Low level as
long as the reference data value is less than or equal to (  ) the counter value and then the pulse is
held to High level for as long as the data value is greater than ( > ) the counter value. One pulse width
is equal to tCLK * 65536.
So, the period and duty times are,
Duty = tCLK * ((T1DR<<8)+T0DR)
Period = tCLK * 65536
In order to generate the PWM0O signal, 3 steps are required,
Steps
Make sure the PWM0O port is set by PWM output mode
Set the T0DR, T1DR value properly
Set the T0SCR register properly
Example C code
T0CONM = 0x03;
T1DR
T0DR
= 1;
= 25;
T0SCR = 0xB8;
Capture Mode
In capture mode, you have to set EXT1 interrupt. When the EXT1 interrupt is occurred, the T0CR and
T1CR register value is loaded into the T0DR and T1DR register and the T0CR and T1CR register is
cleared.
And the timer 0 overflow interrupt is generated whenever the T0CR+T1CR value is overflowed.
So, If you count how many overflow is occurred and read the T0DR+T1DR value in EXT1 interrupt
routine, it is possible to measure the time between two EXT1 interrupts. Or it is possible to measure
the time from the T0 initial time to the EXT1 interrupt occurred time.
The time = (65536* tCLK ) * overflow_count + (tCLK * (T0CR+(T1DR<<8)))
October 19, 2009 Ver.1.35
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