FOD8318 Datasheet, PDF (9/31 Pages) Fairchild Semiconductor – 2.5 A Output Current, IGBT Drive Optocoupler with Active Miller Clamp, Desaturation Detection, and Isolated Fault Sensing

22. This is the amount of time from when the DESAT threshold is exceeded, until the FAULT output goes LOW.
Refer to Figure 54.
23. This is the amount of time the DESAT threshold must be exceeded before V_O begins to go LOW and the FAULT
output to go LOW. Refer to Figure 54.
24. This is the amount of time from when RESET is asserted LOW, until FAULT output goes HIGH. Refer to Figure 54.
25. t_{UVLO ON} UVLO turn-on delay is measured from V_UVLO+ threshold voltage of the output supply voltage (V_DD2) to the
5 V level of the rising edge of the V_O signal.
26. t_{UVLO OFF} UVLO turn-off delay is measured from V_UVLO– threshold voltage of the output supply voltage (V_DD2) to
the 5 V level of the falling edge of the V_O signal.
27. t_GP time to good power is measured from 13.5 V level of the rising edge of the output supply voltage (V_DD2) to the
5 V level of the rising edge of the V_O signal.
28. Common mode transient immunity at output HIGH state is the maximum tolerable negative dVcm / dt on the trailing
edge of the common mode pulse, V_CM, to assure that the output remains in HIGH state (i.e., V_O > 15 V or FAULT
> 2 V).
29.Common mode transient immunity at output LOW state is the maximum positive tolerable dVcm / dt on the leading
edge of the common mode pulse, V_CM, to assure that the output remains in a LOW state (i.e., V_O < 1.0 V or FAULT
< 0.8 V).
©2010 Fairchild Semiconductor Corporation
FOD8318 Rev. 1.1.2
9
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