FOD8318 Datasheet, PDF (8/31 Pages) Fairchild Semiconductor – 2.5 A Output Current, IGBT Drive Optocoupler with Active Miller Clamp, Desaturation Detection, and Isolated Fault Sensing

Switching Characteristics
Apply over all recommended conditions; typical value is measured at V_DD1 = 5 V, V_DD2 – V_SS = 30 V, V_E – V_SS = 0 V,
T_A = 25 °C unless otherwise specified.
Symbol
Parameter
Conditions
Min. Typ. Max. Units ^Figure
t_PHL
Propagation Delay Time to
Logic Low Output⁽¹⁷⁾
t_PLH
Propagation Delay Time to
Logic High Output⁽¹⁸⁾
Rg = 10 ¾, Cg =
10 nF,
f = 10 kHz,
Duty Cycle = 50 %⁽¹⁶⁾
300 500
250 500
ns 17, 18,
19, 20,
ns ^{21, 22,}
43, 51
PWD
PDD Skew
t_R
t_F
t_{DESAT(90 %)}
t_{DESAT(10 %)}
Pulse Width Distortion,
| t_PHL – t_PLH|⁽¹⁹⁾
Propagation Delay Difference
Between Any Two Parts or
Channels, ( t_PHL – t_PLH)⁽²⁰⁾
Output Rise Time (10 % – 90 %)
Output Fall Time (90 % – 10 %)
DESAT Sense to 90 % V_O
Delay⁽²¹⁾
DESAT Sense to 10 % V_O
Delay⁽²¹⁾
Rg = 10 ¾, Cg =
10 nF,
V_DD2 – V_SS = 30 V
50 300 ns
–350
350 ns
34
34
850
2
3
ns 43, 53
ns
ns 23, 44
µs 24, 26,
27, 44
t_DESAT(FAULT) DESAT Sense to Low Level FAULT
Signal Delay⁽²²⁾
1.8
5
µs 25, 44,
54
t_DESAT(LOW) DESAT Sense to DESAT Low
Propagation Delay⁽²³⁾
850
ns
44
t_RESET(FAULT) RESET to High Level FAULT
Signal Delay⁽²⁴⁾
3
6
20 µs 28, 45,
54
PW_RESET
t_{UVLO ON}
t_{UVLO OFF}
t_GP
RESET Signal Pulse Width
UVLO Turn On Delay⁽²⁵⁾
UVLO Turn Off Delay⁽²⁶⁾
Time to Good Power⁽²⁷⁾
V_DD2 = 20 V in
1.0ms Ramp
V_DD2 = 0 to 30 V in
10 µs Ramp
1.2
4
3
30
µs
µs 29, 46
µs
µs 30, 31,
46
| CM_H |
Common Mode Transient
Immunity at Output High
| CM_L |
Common Mode Transient
Immunity at Output Low
T_A = 25 ºC, V_DD1 = 5 V, 35
50
V_DD2 = 25 V,
V_SS = Ground,
V_CM = 1500 V_peak(28)
T_A = 25 ºC, V_DD1 = 5 V, 35
50
V_DD2 = 25 V,
V_SS = Ground,
V_CM = 1500 V_peak(29)
kV/µs 48, 49
kV/µs 47, 50
Notes:
16. This load condition approximates the gate load of a 1200 V / 150 A IGBT.
17. t_PHL propagation delay is measured from the 50 % level on the falling edge of the input pulse (V_IN+, V_IN-) to the 50 %
level of the falling edge of the V_O signal. Refer to Figure 53.
18. t_PHL propagation delay is measured from the 50 % level on the rising edge of the input pulse (V_IN+, V_IN-) to the 50 %
level of the rising edge of the V_O signal. Refer to Figure 53.
19. PWD is defined as | t_PHL – t_PLH | for any given device.
20. The difference between t_PHL and t_PLH between any two FOD8318 parts under same operating conditions, with equal
loads.
21. This is the amount of time the DESAT threshold must be exceeded before V_O begins to go LOW. This is supply
voltage dependent. Refer to Figure 54.
©2010 Fairchild Semiconductor Corporation
FOD8318 Rev. 1.1.2
8
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