FOD8318 Datasheet, PDF (19/31 Pages) Fairchild Semiconductor – 2.5 A Output Current, IGBT Drive Optocoupler with Active Miller Clamp, Desaturation Detection, and Isolated Fault Sensing

Test Circuits (Continued)
LOW to HIGH
+
–
0.1 μF
5V
+
–
3 kΩ
V_FAULT
FOD8318
1 V_IN+
V_E 16
2 V_IN–
V_LED2+ 15
3 V_DD1
DESAT 14
4 GND1
V_DD2 13
5 RESET
V_S 12
6 FAULT
V_O 11
7 V_LED1+
V_CLAMP 10
8 V_LED1-*
V_SS 9
100 pF
0.1 μF
V_O
RL
10 nF
0.1 μF
V_E
+
–
30 V
+
–
*Pin 8 (V_LED1-) is internally connected to pin 4 (GND1).
Figure 44. DESAT Sense (t_{DESAT(90 %)}, t_{DESAT(10 %)}), DESAT Fault (t_DESAT(FAULT)), and (t_DESAT(LOW)) Test Circuit
0.1 μF
5V
+
–
3 kΩ
V_FAULT
FOD8318
1 V_IN+
V_E 16
2 V_IN–
3 V_DD1
V_LED2+ 15
DESAT 14
Strobe 8 V _{0.1 μF}
4 GND1
V_DD2 13
5 RESET
6 FAULT
+
–
7 V_LED1+
8 V_LED1-*
V_S 12
V_O 11
V_CLAMP 10
V_SS 9
V_O
RL
10 nF
0.1 μF
*Pin 8 (V_LED1-) is internally connected to pin 4 (GND1).
Figure 45. Reset Delay (t_RESET(FAULT)) Test Circuit
+
V_{E –}
30 V
+
–
0.1 μF
5V
+
–
3 kΩ
FOD8318
1 V_IN+
V_E 16
2 V_IN–
V_LED2+ 15
3 V_DD1
DESAT 14
4 GND1
V_DD2 13
5 RESET
V_S 12
V_O
6 FAULT
V_O 11
7 V_LED1+
V_CLAMP 10
8 V_LED1-*
V_SS 9
*Pin 8 (V_LED1-) is internally connected to pin 4 (GND1).
0.1 μF
V_E
+
–
0.1 μF
+
V_DD2**
–
**1.0 ms ramp for t_UVLO
10 μs ramp for t_GP
Figure 46. Under-Voltage Lockout Delay (t_UVLO) and Time to Good Power (t_GP) Test Circuit
©2010 Fairchild Semiconductor Corporation
FOD8318 Rev. 1.1.2
19
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