FOD8318 Datasheet, PDF (25/31 Pages) Fairchild Semiconductor – 2.5 A Output Current, IGBT Drive Optocoupler with Active Miller Clamp, Desaturation Detection, and Isolated Fault Sensing

2. Gate Driver Output
A pair of PMOS and NMOS comprise the output driver
stage, which facilitates close to rail-to-rail output swing.
This feature allows a tight control of gate voltage during
on-state and short-circuit condition. The output driver is
typically to sink 2 A and source 2 A at room temperature.
Due to the low R_DS(ON) of the MOSFETs, the power dis-
sipation is reduced as compared to those bipolar-type
driver output stages. The absolute maximum rating of
the output peak current, I_O(PEAK), is 3 A; therefore the
careful selection of the gate resistor, Rg, is required to
limit the short-circuit current of the IGBT.
As shown in Figure 56, gate driver output is influenced
by signals from the photodetector circuitry, the UVLO
comparator, and the DESAT signals. Under no-fault
condition, normal operation resumes while the supply
voltage is above the UVLO threshold, the output of the
photodetector drives the MOSFETs of the output stage.
The logic circuitry of the output stage ensures that the
push-pull devices are never “ON” simultaneously. When
the output of the photodetector is HIGH, the output, V_O,
is pulled to HIGH state by turning on the PMOS. When
the output of the photodetector is LOW, V_O is pulled to
LOW state by turning on the NMOS.
When V_DD2 supply goes below V_UVLO, which is the des-
ignated UVLO threshold at the comparator, V_O is pulled
down to LOW state regardless of photodetector output.
When desaturation is detected, V_O turns off slowly as it
is pulled LOW by the NMOS^1X device. The input to the
fault sense circuitry is latched to HIGH state and turns on
the LED. When V_O goes below 2 V, the NMOS^50X device
turns on again, clamping the IGBT gate firmly to V_SS.
The Fault Sense signal remains latched in the HIGH
state until the LED of the gate driver circuitry turns off.
3. Desaturation Protection, FAULT Output
Desaturation detection protection ensures the protection
of the IGBT at short-circuit by monitoring the collector-
emitter voltage of the IGBT in the half bridge. When the
DESAT voltage goes up and reaches above the thresh-
old voltage, a short-circuit condition is detected and the
driver output stage executes a “soft” IGBT turn-off and is
eventually driven LOW, as illustrated in Figure 58. The
FAULT open-drain output is triggered active LOW to
report a desaturation error. It is only cleared by activating
active LOW by the external controller to the RESET
input with the input logic is pulled to LOW.
The DESAT fault detector should be disabled for a short
period (blanking time) before the IGBT turns on to allow
the collector voltage to fall below DESAT threshold. This
blanking period protects against false trigger of the
DESAT while the IGBT is turning on.
The blanking time is controlled by the internal DESAT
charge current, the DESAT voltage threshold, and the
external DESAT capacitor (capacitor between DESAT
and V_E pin). The nominal blanking time can be calcu-
lated using external capacitance (C_BLANK), FAULT
threshold voltage (V_DESAT), and DESAT charge current
(I_CHG) as:
t_BLANK = C_BLANK x V_DESAT / I_CHG
With a recommended 100 pF DESAT capacitor, the
nominal blanking time is:
100 pF x 7 V / 250 µA = 2.8 µs
4. “Soft” Turn-Off
The soft turn-off feature ensures the safe turn off of the
IGBT under fault conditions. This reduces the voltage
spike on the collector of the IGBT. Without this, the IGBT
would see a heavy spike on the collector and result in
permanent damage to the device.
5. Under-Voltage Lockout
Under-voltage detection prevents the application of
insufficient gate voltage to the IGBT. This could be dan-
gerous, as it would drive the IGBT out of saturation and
into the linear operation where the losses are very high
and quickly overheated. This feature ensures the proper
operating of the IGBTs. The output voltage, V_O, remains
LOW regardless of the inputs as long as the supply volt-
age, V_DD2 – V_E, is less than V_UVLO+. When the supply
voltage falls below V_UVLO- , V_O goes LOW, as illustrated
in Figure 59.
6. Active Miller Clamp Function
An active Miller clamp feature allows the sinking of the
Miller current to the ground or emitter of the IGBT during
a high-dV/dt situation. Instead of driving the IGBT gate to
a negative supply voltage to increase the safety margin,
the device has a dedicated V_CLAMP pin to control the
Miller current. During turn-off, the gate voltage of the
IGBT is monitored and the V_CLAMP output is activated
when the gate voltage goes below 2 V (relative to V_SS).
The Miller clamp NMOS transistor is then turned on and
provides a low resistive path for the Miller current.
This helps prevent a self-turn-on due to the parasitic
Miller capacitor in power switches. The clamp voltage is
V_OL + 2.5 V maximum for a Miller current up to 1200 mA.
In this way, the V_CLAMP function does not affect the turn-
off characteristic. It helps to clamp the gate to the LOW
level throughout the turn-off time. During turn-on, where
the input of the driver is activated, the V_CLAMP function is
disabled or opened.
7. Time to Good Power
At initial power up, the LED is off and the output of the
gate driver should be in the LOW state. Sometimes race
conditions exist that causes the output to follow the V_E
(assuming V_DD2 and V_E are connected externally), until
all of the circuits in the output IC have stabilized. This
condition can result in output transitions or transients
that are coupled to the driven IGBT. These glitches can
cause the high-side and low-side IGBTs to conduct
shoot-through current that may result in destructive
damage to the power semiconductor devices. Fairchild
has introduced a initial turn-on delay, generally called
“time-to-good power”. This delay, typically 30 µs, is only
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FOD8318 Rev. 1.1.2
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