FOD8316 Datasheet, PDF (8/29 Pages) Fairchild Semiconductor – 2.5A Output Current, IGBT Drive Optocoupler

Switching Characteristics (Continued)
Apply over all recommended conditions, typical value is measured at V_DD1 = 5V, V_DD2 – V_SS = 30V, V_E – V_SS = 0V,
T_A = 25°C unless otherwise specified.
Symbol
t_GP
| CM_H |
Parameter
Time to Good Power⁽²⁷⁾
Common Mode Transient
Immunity at Output High
| CM_L |
Common Mode Transient
Immunity at Output Low
Conditions
V_DD2 = 0 to 30V in
10µs Ramp
T_A = 25ºC, V_DD1 = 5V,
V_DD2 = 25V,
V_SS = Ground,
V_CM = 1500Vpk⁽²⁸⁾
T_A = 25ºC, V_DD1 = 5V,
V_DD2 = 25V,
V_SS = Ground,
V_CM = 1500Vpk⁽²⁹⁾
Min.
35
Typ.
30
50
Max. Units Figure
µs 30, 31,
43
kV/µs 45, 46
35
50
kV/µs 44, 47
Notes:
16. This load condition approximates the gate load of a 1200 V/150A IGBT.
17. t_PHL propagation delay is measured from the 50% level on the falling edge of the input pulse(V_IN+, V_IN-) to the 50%
level of the falling edge of the V_O signal. Refer to Figure 48.
18. t_PHL propagation delay is measured from the 50% level on the rising edge of the input pulse (V_IN+, V_IN-) to the 50%
level of the rising edge of the V_O signal. Refer to Figure 48.
19. PWD is defined as | t_PHL – t_PLH | for any given device.
20. The difference between t_PHL and t_PLH between any two FOD8316 parts under same operating conditions, with equal
loads.
21. This is the amount of time the DESAT threshold must be exceeded before V_O begins to go low. This is supply voltage
dependent. See Figure 49.
22. This is the amount of time from when the DESAT threshold is exceeded, until the FAULT output goes low.
See Figure 49.
23. This is the amount of time the DESAT threshold must be exceeded before V_O begins to go low, and the FAULT
output to go low. See Figure 49.
24. This is the amount of time from when RESET is asserted low, until FAULT output goes high. See Figure 49.
25. t_{UVLO ON} UVLO Turn On Delay is measured from V_UVLO+ threshold voltage of the output supply voltage (V_DD2) to
the 5V level of the rising edge of the V_O signal.
26. t_{UVLO OFF} UVLO Turn Off Delay is measured from V_UVLO– threshold voltage of the output supply voltage (V_DD2) to
the 5V level of the falling edge of the V_O signal.
27. t_GP Time to Good Power is measured from 13.5V level of the rising edge of the output supply voltage (V_DD2) to the
5V level of the rising edge of the V_O signal.
28. Common mode transient immunity at output high state is the maximum tolerable negative dVCM/dt on the trailing
edge of the common mode pulse, V_CM, to assure that the output will remain in the high state (i.e., V_O > 15 V or
FAULT > 2 V).
29.Common mode transient immunity at output low state is the maximum positive tolerable dVCM/dt on the leading
edge of the common mode pulse, V_CM, to assure that the output will remain in a low state (i.e., V_O < 1.0 V or FAULT
< 0.8 V).
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.0
8
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