FOD8316 Datasheet, PDF (7/29 Pages) Fairchild Semiconductor – 2.5A Output Current, IGBT Drive Optocoupler

Electrical Characteristics (Continued)
Apply over all recommended conditions, typical value is measured at V_DD1 = 5V, V_DD2 – V_SS = 30V, V_E – V_SS = 0V,
T_A = 25°C unless otherwise specified.
Symbol
Parameter
Conditions
Min.
Typ.
Max. Units Figure
V_UVLO+
V_UVLO-
UVLO_HYS
V_DESAT
Under Voltage Lockout
Threshold⁽¹⁴⁾
Under Voltage Lockout
Threshold Hysteresis
DESAT Threshold⁽¹⁴⁾
V_O > 5V @ 25°C
V_O < 5V @ 25°C
@ 25°C
11.5
13.5
V 15, 29,
9
10
V
39
0.4
1.5
V
V_DD2 – V_E > V_ULVO-,
6.0
7.0
9.0
V 16, 38
V_O < 5V
Notes:
10. Maximum pulse width = 10µs, maximum duty cycle = 0.2%.
11. Maximum pulse width = 4.99ms, maximum duty cycle = 99.8%.
12. V_OH is measured with the DC load current in this testing (Maximum pulse width = 1ms,
Maximum duty cycle = 20%).When driving capacitive loads, V_OH will approach V_DD as I_OH approaches zero units.
13. Positive Output supply voltage (V_DD2 – V_E) should be at least 15V. This is to ensure adequate margin in excess of
the maximum Under Voltage Lockout Threshold V_UVLO+ of 13.5V.
14. When V_DD2 – V_E > V_UVLO and output state V_O of the FOD8316 is allowed to go high, the DESAT detection feature
will be active and will provide the primary source of IGBT protection. UVLO is needed to ensure DESAT detection
is functional.
15. The blanking time, t_BLANK is adjustable by an external capacitor (C_BLANK) where t_BLANK = C_BLANK * (V_DESAT/I_CHG)
Switching Characteristics
Apply over all recommended conditions, typical value is measured at V_DD1 = 5V, V_DD2 – V_SS = 30V, V_E – V_SS = 0V,
T_A = 25°C unless otherwise specified.
Symbol
t_PHL
t_PLH
PWD
PDD Skew
t_R
t_F
t_DESAT(90%)
t_DESAT(10%)
Parameter
Propagation Delay Time to
Logic Low Output⁽¹⁷⁾
Propagation Delay Time to
Logic High Output⁽¹⁸⁾
Pulse Width Distortion,
| t_PHL – t_PLH|⁽¹⁹⁾
Propagation Delay Difference
Between Any Two Parts or
Channels, ( t_PHL – t_PLH)⁽²⁰⁾
Output Rise Time (10% – 90%)
Output Fall Time (90% – 10%)
DESAT Sense to 90% V_O Delay⁽²¹⁾
DESAT Sense to 10% V_O Delay⁽²¹⁾
Conditions
Rg = 10Ω, Cg = 10nF,
f = 10kHz,
Duty Cycle = 50%⁽¹⁶⁾
Rg = 10Ω, Cg = 10nF,
V_DD2 – V_SS = 30V
t_DESAT(FAULT)
t_DESAT(LOW)
t_RESET(FAULT)
PW_RESET
t_{UVLO ON}
t_{UVLO OFF}
DESAT Sense to Low Level FAULT
Signal Delay⁽²²⁾
DESAT Sense to DESAT Low
Propagation Delay⁽²³⁾
RESET to High Level FAULT Signal
Delay⁽²⁴⁾
RESET Signal Pulse Width
UVLO Turn On Delay⁽²⁵⁾
UVLO Turn Off Delay⁽²⁶⁾
V_DD2 = 20V in
1.0ms Ramp
Min.
Typ.
300
250
Max. Units Figure
500 ns 17, 18,
19, 20,
500 ns ^{21, 22,}
40, 48
50 300 ns
–350
350 ns
34
ns 40, 48
34
ns
850
ns 23, 41
2
3
µs 24, 26,
27, 41
1.8
5
µs 25, 41,
49
850
ns
41
3
6
20 µs 28, 42,
49
1.2
µs
4
µs 29, 43
3
µs
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.0
7
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