FOD8316 Datasheet, PDF (18/29 Pages) Fairchild Semiconductor – 2.5A Output Current, IGBT Drive Optocoupler

Test Circuits (Continued)
Low to High
+
–
0.1μF
5V
+
–
3K
V_FAULT
FOD8316
1 V_IN+
V_E 16
2 V_IN–
V_LED2+ 15
3 V_DD1
DESAT 14
4 GND1
V_DD2 13
5 RESET
V_S 12
6 FAULT
V_O 11
7 V_LED1+
V_SS 10
8 V_LED1-*
V_SS 9
100pF
V_O
RL
10nF
0.1μF
0.1μF
+
V_{E –}
30V
+
–
*Pin 8 (V_LED1-) is internally connected to pin 4 (GND1).
Figure 41. DESAT Sense (t_DESAT(90%), t_DESAT(10%)), DESAT Fault (t_DESAT(FAULT)), and (t_DESAT(LOW)) Test Circuit
0.1μF
5V
+
–
3K
V_FAULT
FOD8316
1 V_IN+
V_E 16
2 V_IN–
3 V_DD1
V_LED2+ 15
DESAT 14
Strobe 8V _0.1μF
+
V_{E –}
4 GND1
V_DD2 13
5 RESET
6 FAULT
+
–
7 V_LED1+
8 V_LED1-*
V_S 12
V_O 11
V_SS 10
V_SS 9
V_O
RL
10nF
0.1μF
30V
+
–
*Pin 8 (V_LED1-) is internally connected to pin 4 (GND1).
Figure 42. Reset Delay (t_RESET(FAULT)) Test Circuit
0.1μF
5V
+
–
3K
FOD8316
1 V_IN+
V_E 16
2 V_IN–
V_LED2+ 15
3 V_DD1
DESAT 14
4 GND1
V_DD2 13
5 RESET
V_S 12
V_O
6 FAULT
V_O 11
7 V_LED1+
V_SS 10
8 V_LED1-*
V_SS 9
*Pin 8 (V_LED1-) is internally connected to pin 4 (GND1).
0.1μF
+
V_{E –}
0.1μF
+
V_DD2**
–
**1.0ms ramp for t_UVLO
10μs ramp for t_GP
Figure 43. Under Voltage Lockout Delay (t_UVLO) and Time to Good Power (t_GP) Test Circuit
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.0
18
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