FAB2200 Datasheet, PDF (8/33 Pages) Fairchild Semiconductor – Audio Subsystem with Stereo Class-G Headphone Amplifier and 1.2W Mono Class-D Speaker Amplifier

I²C DC Electrical Characteristics
Unless otherwise noted, V_BATT = 2.80V to 5.25V and T_A = -40°C to 85°C.
Symbol
Parameter
V_IL Low-Level Input Voltage
V_IH High-Level Input Voltage
V_OL Low-level Output Voltage
I_IH
High-Level Input Current
I_IL
Low-Level Input Current
Conditions
V_BATT 2.80V to 5.25V
V_BATT 2.80V to 5.25V
at 3mA Sink Current
(Open-Drain or Open-Collector)
Each I/O Pin, Input Voltage = V_BATT
Each I/O Pin, Input Voltage = 0V
Fast Mode (400kHz)
Min.
Max. Unit
-0.3
0.6
V
1.3
V
0
0.4
V
-1
1
µA
-1
1
µA
I²C AC Electrical Characteristics
Unless otherwise noted, V_BATT = 2.80V to 5.25V and T_A = -40°C to 85°C.
Symbol
Parameter
Fast Mode
Min.
Max. Unit
f_SCL SCL Clock Frequency
0
400
kHz
t_HD;STA Hold Time (Repeated) START Condition
0.6
µs
t_LOW LOW Period of SCL Clock
1.3
µs
t_HIGH HIGH Period of SCL Clock
0.6
µs
t_SU;STA Set-up Time for Repeated START Condition
0.6
µs
t_HD;DAT
t_SU;DAT
t_r
t_f
Data Hold Time
Data Set-up Time⁽⁴⁾
Rise Time of SDA and SCL Signals⁽⁵⁾
Fall Time of SDA and SCL Signals⁽⁵⁾
0
0.9
µs
100
ns
20+0.1C_b
300
ns
20+0.1C_b
300
ns
t_SU;STO Set-up Time for STOP Condition
0.6
µs
t_BUF Bus Free Time between STOP and START Conditions
1.3
µs
t_SP Pulse Width of Spikes that Must Be Suppressed by the Input Filter
0
50
ns
Notes:
4. A fast-mode I²C-Bus^® device can be used in a standard-mode system, but the requirement t_SU;DAT ≥250ns must
then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If
such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
t_{r_max} + t_SU;DAT = 1000 + 250 = 1250ns (according to the standard-mode I²C bus specification) before the SCL line
is released.
5.
C_b equals the total
allowed according
capacitance of one bus
to the I²C specification.
line
in
pf.
If
mixed
with
high-speed
mode
devices,
faster
fall
times
are
Figure 3. Definition of Timing for Full-Speed Mode Devices on the I²C-Bus^®
© 2009 Fairchild Semiconductor Corporation
FAB2200 • Rev. 1.0.1
8
www.fairchildsemi.com