FAB2200 Datasheet, PDF (12/33 Pages) Fairchild Semiconductor – Audio Subsystem with Stereo Class-G Headphone Amplifier and 1.2W Mono Class-D Speaker Amplifier

Functional Description
Shutdown Mode
When SHDNB bit is set to 0 or the SDB pin is grounded,
the FAB2200 enters low-power Shutdown Mode.
While SHDNB=0 and SDB is HIGH, I²C communication
is available. I²C values are preserved. Values are not
reset on exiting Shutdown Mode.
If the SDB pin is grounded, I²C communication is
unavailable. I²C values are not preserved. Values are
reset to default values after SDB goes HIGH.
Inputs During Shutdown
To achieve low supply current during shutdown, all
inputs must be at DC levels (except the BYPASS pins).
Audio
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must be
pins must
be grounded or pulled HIGH with no toggling. If AC is
presented to the inputs during shutdown, standby
current may increase slightly, but there are no other
negative effects.
Thermal Shutdown
If the junction temperature of the device exceeds the
thermal shutdown threshold (see Electrical Characteristics
table), the device protects itself by shutting down. The
device remains shut down until the junction temperature
falls below the thermal shutdown hysteresis.
The I²C port remains functional and the OVRTEMP bit is
set to O. This bit remains set until it is read. If the device
is still in thermal shutdown when the bit is read, it
remains set to 1. Otherwise, the bit is cleared to 0.
Over-Current Shutdown
If the output current limit of either amplifier is exceeded
(see the Electrical Characteristics table), the amplifier in
question shuts down for approximately one second.
After one second, the amplifier is re-enabled. If the
amplifier output current exceeds the limit again, the
cycle repeats.
During current-limit shutdown, the I²C port remains
functional. If the current-limit shutdown was caused by
the speaker amplifier, the OVRCURSP bit is set to 1. This
bit remains set until it is read. If the speaker amplifier is
still in current-limit shutdown when the bit is read, it
remains set to 1. Otherwise, the bit is cleared to 0.
Signal Path
The input channels have a pre-amplifier stage that can
be set from 0dB to 21dB of gain. The headphone
amplifiers have separate volume controls that range
from -53dB to 6dB. The speaker amplifier has a volume
control that ranges from -25dB to 6dB. In addition, the
speaker amplifier has a fixed gain of 6dB.
A variety of combinations of these signals can be routed
to the headphone amplifiers or the speaker amplifier
(see Table 1). For example, to connect the left
headphone amplifier channel to IN3 and IN1, set the
SELHPL3 and SELHPL1 bits to 1. SELHPL4 and
SELHPL2 should be set to 0.
The DIFFIN43 and DIFFIN21 bits configure the inputs
as differential pairs. When configured as differential, the
even-numbered selection bit should be 1 and the odd-
numbered selection bit should be 0. For example, if
channels 4 and 3 are a differential pair that should be
connected to the speaker amplifier, DIFFIN43 and
SELSPA4 should be set to 1. SELSPA3, SELSPA2, and
SELSPA1 should be set to 0.
Amplifier channels that have no inputs selected should
be muted (HPxVOL = 00000 or STARTGAIN = 000000).
If an amplifier channel has no input selection bits set to
1, the amplifier channel is turned off. When the speaker
amplifier is turned off, the SPKRP and SPKRN outputs
stop switching.
Unused audio input pins must be AC grounded.
An integrated Dual-Pole Single-Throw (DPST) analog
bypass switch can be used to route system audio
signals. For example, baseband audio can be routed to
the speaker by connecting the BYPOUTx pins to the
SPKRx pins. Baseband audio outputs would then be
connected to the BYPINx pins through optional external
resistors if the baseband device expects a higher
impedance than the existing speaker.
Gain for the headphone amplifier signal path is defined
by PGAINxx + HPxVOL.
Gain for the speaker amplifier signal path is defined by
PGAINxx + PRESENTGAIN + 6dB.
Internal signal amplitude should not exceed 2.3V_PP.
Extra caution should be taken when mixing signals. For
example, if IN1 is mixed with IN3, the maximum peak to
peak amplitude of IN1 plus the maximum peak to peak
amplitude of IN3 should not exceed 2.3V_PP.
© 2009 Fairchild Semiconductor Corporation
FAB2200 • Rev. 1.0.1
12
www.fairchildsemi.com