FAB2200 Datasheet, PDF (22/33 Pages) Fairchild Semiconductor – Audio Subsystem with Stereo Class-G Headphone Amplifier and 1.2W Mono Class-D Speaker Amplifier

I²C Control
Writing to and reading from the FAB2200 registers is
accomplished via the I²C interface. The I²C protocol
requires that one device on the bus initiates and
controls all read and write operations. This device is
called the “master” device. The master device also
generates the SCL signal, which is the clock signal for
all other devices on the bus, called “slave” devices. The
FAB2200 is a slave device. Both the master and slave
devices can send and receive data on the bus.
During I²C operations, one data bit is transmitted per
clock cycle. All I²C operations follow a repeating nine-
clock-cycle pattern that consists of eight bits (one byte)
of transmitted data followed by an acknowledge (ACK)
or not acknowledge (NACK) from the receiving device.
Note that there are no unused clock cycles during any
operation – therefore, there must be no breaks in the
stream of data and ACKs/NACKs during data transfers.
For most operations, I²C protocol requires the SDA line
to remain stable (unmoving) whenever SCL is HIGH;-
i.e., transitions on the SDA line can only occur when
SCL is LOW. The exceptions to this rule are when the
master device issues a START or STOP condition. A
slave device cannot issue a START or STOP condition.
START Condition: This condition occurs when the SDA
line transitions from HIGH to LOW while SCL is HIGH.
The master device uses this condition to indicate that a
data transfer is about to begin.
STOP Condition: This condition occurs when the SDA
line transitions from LOW to HIGH while SCL is HIGH.
The master device uses this condition to signal the end
of a data transfer.
Acknowledge and Not Acknowledge: When data is
transferred to the slave device, it sends an acknowledge
(ACK) after receiving every byte of data. The receiving
(slave) device sends an ACK by pulling SDA LOW for
one clock cycle.
When the master device is reading data from the slave
device, the master sends an ACK after receiving every
byte of data. Following the last byte, a master device
sends a “not acknowledge” (NACK) instead of an ACK,
followed by a STOP condition. A NACK is indicated by
leaving SDA HIGH during the clock after the last byte.
Slave Address
Each slave device on the bus has a unique address so
the master can identify which device is sending or
receiving data. The FAB2200 slave address is
1001101X binary where “X” is the read/write bit. Master
write operations are indicated when X=0. Master read
operations are indicated when X=1.
Writing to and Reading from the FAB2200
All read and write operations must begin with a START
condition generated by the master device. After the
START condition, the master device must immediately
send a slave address (7 bits), followed by a read/write
bit. If the slave address matches the address of the
FAB2200, the FAB2200 sends an ACK by pulling the
SDA line LOW for one clock cycle.
Setting the Pointer
For all operations, the pointer stored in the command
register must be pointing to the register that is going to
be written to or read from. To change the pointer value
in the Command register, the read/write bit following the
address must be 0. This indicates that the master writes
new information into the Command register.
After the FAB2200 sends an ACK in response to
receiving the address and read/write bit, the master
device must transmit an appropriate 8-bit pointer value,
as explained in the I²C Registers section. The FAB2200
sends an ACK after receiving the new pointer data.
The pointer set operation is illustrated in Figure 25 and
Figure 26. Any time a pointer set is performed, it must
be immediately followed by a read or write operation.
The Command register retains the current pointer value
between operations; therefore subsequent read
operations do not require a pointer set cycle. Write
operations always require the pointer be reset.
Reading
If the pointer is already pointing to the desired register,
the master can read from that register by setting the
read/write bit (following the slave address) to 1. After
sending an ACK, FAB2200 begins transmitting data
during the following clock cycle. The master should
respond with a NACK, followed by a STOP condition
(see Figure 23).
The master reads multiple bytes by responding to the
data with an ACK instead of a NACK and continuing to
send SCL pulses, as shown in Figure 24. The FAB2200
increments the pointer by one and sends the data from
the next register. The master indicates the last data byte
by responding with a NACK, followed by a STOP.
To read from a register other than the one currently
indicated by the Command register, a pointer to the
desired register must be set. Immediately following the
pointer set, the master must perform a REPEAT START
condition (see Figure 26), which indicates to the
FAB2200 that a new operation is about to occur. If the
REPEAT START condition does not occur, the
FAB2200 assumes that a write is taking place and the
selected register is overwritten by the upcoming data on
the data bus. After the START condition, the master
must again send the device address and read/write bit.
This time, the read/write bit must be set to 1 to indicate
a read. The rest of the read cycle is the same as
described in the previous paragraphs for reading from a
preset pointer location.
© 2009 Fairchild Semiconductor Corporation
FAB2200 • Rev. 1.0.1
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