FIN24A Datasheet, PDF (7/20 Pages) Fairchild Semiconductor – Low Voltage 24-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges (Preliminary)

Preliminary
Embedded Word Clock Operation
The FIN24A sends and receives serial data source syn-
chronously with a bit clock. The bit clock has been modified
to create a word boundary at the end of each data word.
The word boundary has been implemented by skipping a
low clock pulse. This appears in the serial clock stream as
3 consecutive bit times where signal CKSO remains HIGH.
In order to implement this sort of scheme two extra data
bits are required. During the word boundary phase the data
will toggle either HIGH-then-LOW or LOW-then-HIGH
dependent upon the last bit of the actual data word. Table 2
provides some examples showing the actual data word and
the data word with the word boundary bits added. Note that
a 24-bit word will be extended to 26-bits during serial trans-
mission. Bit 25 and Bit 26 are defined with-respect-to Bit
24. Bit 25 will always be the inverse of Bit 24, and Bit 26
will always be the same as Bit 24. This insures that a
“0” o “1” and a “1” o “0” transition will always occur during
the embedded word phase where CKSO is HIGH.
The serializer generates the word boundary data bits and
the boundary clock condition and embeds them into the
serial data stream. The deserializer looks for the end of the
word boundary condition to capture and transfer the data to
the parallel port. The deserializer only uses the embedded
word boundary information to find and capture the data.
These boundary bits are then stripped prior to the word
being sent out of the parallel port.
Hex
3FFFFFh
155555h
xxxxxxh
TABLE 2. Word Boundary Data Bits
24-Bit Data Words
Binary
0011 1111 1111 1111 1111 1111b
0101 0101 0101 0101 01010 0101b
0xxx xxxx xxxx xxxx xxxx xxxxb
24-Bit Data Word with Word Boundary
Hex
Binary
1FFFFFFh 01 1111 1111 1111 1111 1111 1111b
1155555h 01 0101 0101 0101 0101 0101 0101b
1xxxxxxh 01 0xxx xxxx xxxx xxxx xxxx xxxxb
LVCMOS Data I/O
The LVCMOS input buffers have a nominal threshold value
equal to ½ of V_DDP. The input buffers are only operational
when the device is operating as a serializer. When the
device is operating as a deserializer the inputs are gated
off to conserve power.
The LVCMOS 3-STATE output buffers are rated for a
source/sink current of 2 mAs at 1.8V. The outputs are
active when the DIRI signal is asserted LOW. When the
DIRI signal is asserted HIGH the bi-directional LVCMOS
I/Os will be in a HIGH-Z state. Under purely capacitive load
conditions the output will swing between GND and V_DDP.
The LVCMOS I/O buffers incorporate bushold functionality
to allow for pins to maintain state when they are not driven.
The bushold circuitry only consumes power during signal
transitions.
Differential I/O Circuitry
The differential I/O circuitry is a low power variant of LVDS.
The differential outputs operate in the same fashion as
LVDS by sourcing and sinking a balanced current through
the output pair. Like LVDS an input source termination
resistor is required to develop a voltage at the differential
input pair. The FIN24A device incorporates an internal ter-
mination resistor on the CKSI receiver and a gated internal
termination resistor on the DS input receiver. The gated ter-
mination resistor insures proper termination regardless of
direction of data flow.
During power-down mode the differential inputs will be dis-
abled and powered down and the differential outputs will be
placed in a HIGH-Z state.
FIGURE 6. LVCMOS I/O
FIGURE 7. Bi-directional Differential I/O Circuitry
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