FIN24A Datasheet, PDF (13/20 Pages) Fairchild Semiconductor – Low Voltage 24-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges (Preliminary)

Control Logic Timing Controls
Symbol
t_{PHL_DIR},
t_{PLH_DIR}
t_PLZ,
t_PHZ
t_PZL,
t_PZH
t_PLZ,
t_PHZ
t_PZL,
t_PZH
t_PLZ,
t_PHZ
t_PZL,
t_PZH
Parameter
Propagation Delay
DIRI-to-DIRO
Propagation Delay
DIRI-to-DP
Propagation Delay
DIRI-to-DP
Deserializer Disable Time:
S0 or S1 to DP
Deserializer Enable Time:
S0 or S1 to DP
Serializer Disable Time:
S0 or S1 to CKSO, DS
Serializer Enable Time:
S0 or S1 to CKSO, DS
Capacitance
Test Conditions
DIRI LOW-to-HIGH or HIGH-to-LOW
DIRI LOW-to-HIGH
DIRI HIGH-to-LOW
DIRI 0,
S1(2) 0 and S2(1) LOW-to-HIGH Figure 26
DIRI 0,
S1(2) 0 and S2(1) LOW-to-HIGH Figure 26
DIRI 1,
S1(2) 0 and S2(1) HIGH-to-LOW Figure 25
DIRI 1,
S1(2) and S2(1) LOW-to-HIGH Figure 25
Min
TBD
Symbol
Parameter
Test Conditions
Min
C_IN
Capacitance of Input Only Signals, DIRI 1, S1 0,
CKREF, STROBE, S1, S2, DIRI
V_DD 2.5V
C_IO
Capacitance of Parallel Port Pins
DIRI 1, S1 0,
DP_1:12
V_DD 2.5V
C_IO-DIFF
Capacitance of Differential I/O Signals DIRI 0, PwnDwn 0;
S1 0, V_DD 2.5V
Preliminary
Typ
TBD
Max
Units
7.0
ns
7.0
ns
10.0
ns
7.0
ns
10.0
ns
7.0
ns
10.0
ns
Typ
TBD
TBD
TBD
Max
Units
pF
pF
pF
13
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