FIN24A Datasheet, PDF (12/20 Pages) Fairchild Semiconductor – Low Voltage 24-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges (Preliminary)

Preliminary
AC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Serializer Electrical Characteristics
t_TCP
CKREF Clock Period
(2 MHz - 30 MHz)
See Figure 17 S2 0 S1 1
200
500
CKREF
STROBE
S2 1 S1 0
66.0
T
200
ns
S2 1 S1 1
33.0
100
f_REF
CKREF Frequency Relative
to Strobe Frequency
CKREF
does not equal
STROBE
S2 0 S1 1
S2 1 S1 0
S2 1 S1 1
1.1 *f_ST
5.0
15.0
MHz
30.0
t_CPWH
t_CPWL
t_CLKT
t_SPWH
t_SPWL
f_MAX
CKREF Clock High Time
CKREF Clock Low Time
LVCMOS Input Transition Time
STROBE Pulse Width HIGH
STROBE Pulse Width LOW
Maximum Serial Data Rate
TBD
0.5
TBD
T
TBD
0.5
TBD
T
See Figure 17
TBD
ns
See Figure 17
5.0
ns
See Figure 17
5.0
ns
CKREF x 26
S2 0 S1 1
52.0
130
S2 1 S1 0
130
390
Mb/s
S2 1 S1 1
260
780
Serializer AC Electrical Characteristics
t_TLH
t_THL
t_STC
t_HTC
t_TCCD
Differential Output Rise Time (20% to 80%)
Differential Output Fall Time (80% to 20%)
DP[n] Setup to STROBE
DP[n] Hold to STROBE
Transmitter Clock Input to
Clock Output Delay
See Figure 14
DIRI 1
See Figure 16 (f 10 MHz)
See Figure 20, DIRI 1,
CKREF STROBE
0.6
0.9
ns
0.6
0.9
ns
2.5
ns
0
ns
TBD
TBD
TBD
ns
t_SPOS
CKSO Position Relative to DS
See Figure 23, (Note 5)
CKREF Serialization Mode
TBD
TBD
TBD
See Figure 23, (Note 5)
No CKREF Serialization Mode
TBD
TBD
TBD
PLL AC Electrical Characteristics Specifications
t_JCC
t_TPLLS0
CKSO Clock Out Jitter (Cycle-to-Cycle)
Serializer Phase Lock Loop Stabilization
Time
(Note 6)
See Figure 19
TBD
1000
ns
Cycles
t_TPLLD0
PLL Disable Time Loss of Clock
See Figure 24, (Note 7)
3.0
t_TPLLD1
PLL Power-Down Time
See Figure 25
Deserializer AC Electrical Characteristics
10.0
us
20.0
ns
t_{S_DS}
Serial Port Setup Time, DS-to-CKSI
Figure 22, (Note 8)
500
ps
t_{H_DS}
Serial Port Hold Time, DS-to-CKS
Figure 22, (Note 8)
500
ps
t_RCOP
Deserializer Clock Output (CKP OUT) Period Figure 18
33.0
T
500
ns
t_RCOL
t_RCOH
CKP OUT Low Time
CKP OUT High Time
Figure 18 (Rising Edge Strobe)
Serializer Source STROBE CKREF
Where a (1/f)/26 (Note 9)
13a-3
13a-3
13a3
ns
13a3
ns
t_PDV
Data Valid to CKP LOW
Figure 18 (Rising Edge Strobe)
Where a (1/f)/26 (Note 9)
6a-3
6a
6a3
ns
t_ROLH
Output Rise Time (20% to 80%)
C_L 8 pF
2.5
5.0
ns
t_ROHL
Output Fall time (80% to 20%)
Figure 15
2.5
5.0
ns
Note 5: Skew is measured from either the rising or falling edge of the clock (CKSO) relative to the center of the data bit (DSO). Both outputs should have
identical load conditions for this to be valid.
Note 6: This jitter specification is based on the assumption that PLL has a REF Clock with cycle-to-cycle input jitter less than 2ns.
Note 7: The power-down time is a function of the CKREF frequency prior to CKREF being stopped HIGH or LOW and the state of the S1/S2 mode pins. The
specific number of clock cycles required for the PLL to be disabled will vary dependent upon the operating mode of the device.
Note 8: Signals are transmitted from the serializer source synchronously. Note that in some cases data is transmitted when the clock remains at a high state.
Skew should only be measured when data and clock are transitioning at the same time. Total measured input skew would be a combination of output skew
from the serializer, load variations and ISI and jitter effects.
Note 9: Rising edge of CKP will appear approximately 13 bit times after the falling edge of the CKP output. Falling edge of CKP will occur approximately 6 bit
times after a data transition. Variation with respect to the CKP signal is due to internal propagation delays of the device. Note that if CKREF is not equal to
STROBE for the serializer the CKP signal will not maintain a 50% Duty Cycle. The low time of CKP will remain 13 bit times.
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