FIN24A Datasheet, PDF (6/20 Pages) Fairchild Semiconductor – Low Voltage 24-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges (Preliminary)

Preliminary
Deserializer Operation Mode
The operation of the deserializer is only dependent upon
the data received on the DSI data signal pair and the CKSI
clock signal pair. The following two sections describe the
operation of the deserializer under two distinct serializer
source conditions. References to the CKREF and STROBE
signals refer to the signals associated with the serializer
device used in generating the serial data and clock signals
that are inputs to the deserializer.
When operating in this mode the internal serializer circuitry
is disabled including the parallel data input buffers. If there
is a CKREF signal provided then the CKSO serial clock will
continue to transmit bit clocks.
Deserializer Operation:
DIRI equals 0
(Serializer Source: CKREF equals STROBE)
When the DIRI signal is asserted LOW the device will be
configured as a deserializer. Data will be captured on the
serial port and deserialized through use of the bit clock
sent with the data. The word boundary is defined in the
actual clock and data signal. Parallel data will be generated
at the time the word boundary is detected. The falling edge
of CKP will occur approximately 6 bit times after the falling
edge of CKSI. The rising edge of CKP will go high approxi-
mately 13 bit times after CKP goes LOW. The rising edge
of CKP will be generated approximately 13 bit times later.
When no embedded word boundary occurs then no pulse
on CKP will be generated and CKP will remain HIGH.
Deserializer Operation:
DIRI equals 0
(Serializer Source: CKREF does not equal STROBE)
The logical operation of the deserializer remains the same
regardless of if the CKREF is equal in frequency to the
STOBE or at a higher frequency than the STROBE. The
actual serial data stream presented to the deserializer will
however be different because it will have non-valid data
bits sent between words. The duty cycle of CKP will vary
based on the ratio of the frequency of the CKREF signal to
the STROBE signal. The frequency of the CKP signal will
be equal to the STROBE frequency. The falling edge of
CKP will occur 6 bit times after the data transition. The
LOW time of the CKP signal will be equal to ½ (13 bit
times) of the CKREF period. The CKP HIGH time will be
equal to STROBE period – ½ of the CKREF period. Figure
5 is representative of a waveform that could be seen when
CKREF is not equal to STROBE. If CKREF was signifi-
cantly faster then additional non-valid data bits would occur
between data words.
FIGURE 4. Deserializer Timing Diagram
(Serializer Source: CKREF equals STROBE)
FIGURE 5. Deserializer Timing Diagram
(Serializer Source: CKREF does not equal STROBE)
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