FIN24A Datasheet, PDF (14/20 Pages) Fairchild Semiconductor – Low Voltage 24-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges (Preliminary)

AC Loading and Waveforms
Preliminary
FIGURE 11. Differential LpLVDS Output DC Test Circuit
Note A: For All input pulses, t_R or t_F  1 ns
FIGURE 12. Differential Receiver Voltage Definitions
Note: The Worst Case test pattern produces a maximum toggling of internal digital circuits, LpLVDS I/O and LVCMOS I/O with the PLL operating at the ref-
erence frequency unless otherwise specified. Maximum power is measured at the maximum V_DD values. Minimum values are measured at the minimum V_DD
values. Typical values are measured at V_DD 2.5V.
FIGURE 13. “Worst Case” Serializer Test Pattern
FIGURE 14. LpLVDS Output Load
and Transition Times
FIGURE 15. LVCMOS Output Load
and Transition Times
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