FIN24A Datasheet, PDF (10/20 Pages) Fairchild Semiconductor – Low Voltage 24-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges (Preliminary)

Preliminary
Absolute Maximum Ratings(Note 2)
Supply Voltage (V_DD)
ALL Input/Output Voltage
LVDS Output Short Circuit Duration
Storage Temperature Range (T_STG)
Maximum Junction Temperature (T_J)
Lead Temperature (T_L)
(Soldering, 4 seconds)
ESD Rating
Human Body Model, 1.5K:, 100pF
Machine Model, 0:, 200pF
0.5V to 4.6V
0.5V to 4.6V
Continuous
65qC to 150qC
150qC
260qC
!2kV
!200V
Recommended Operating
Conditions
Supply Voltage (V_DDA, V_DDS)
Supply Voltage (V_DDP)
Operating Temperature (T_A) (Note 2)
Supply Noise Voltage (V_DDA-PP)
2.775V r 5.0%V
1.65V to 3.6V
10qC to  70qC
100 mV_P-P
Note 2: Absolute maximum ratings are DC values beyond which the device
may be damaged or have its useful life impaired. The datasheet specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading vari-
ables. Fairchild does not recommend operation outside datasheet specifi-
cations.
DC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
(Note 3)
LVCMOS I/O
V_IH
Input High Voltage
V_IL
Input Low Voltage
V_OH
Output High Voltage
V_OL
Output Low Voltage
I_IN
I_I(Hold)
Input Current
Minimum Bushold Currents
I_I(OD)
I_OFF
Minimum Required Bushold
Overdrive Current
Input/Output Power-Off
Leakage Current
0.65 x V_DDP
GND
V_DDP 3.3 r 0.3
I_OH 2.0 mA
V_DDP 2.5 r 0.2
V_DDP 1.8 r 0.15
V_DDP 3.3 r 0.3
I_OL 2.0 mA
V_DDP 2.5 r 0.2
V_DDP 1.8 r 0.15
V_IN 0V to 3.6V
V_DDP 3.0, V_IN 1.95 or 1.05
V_DDP 2.3, V_IN 1.495 or 0.805
V_DDP 1.65, V_IN 1.07 or 0.58
V_DDP 3.6, V_IN 2.34 or 1.26
V_DDP 2.7, V_IN 1.76 or 0.945
V_DDP 1.95, V_IN 1.268 or 0.682
V_DDP 0V, V_DDS 0, V_DDA 0
ALL LVCMOS Inputs/ Outputs 0V to 3.6V
0.75 x V_DDP
5.0
r35.0
r25.0
r10.0
r200
r150
r75.0
V_DDP
0.35 x V_DDP
V
V
0.25 x V_DDP
V
5.0
PA
uA
uA
r5.0
PA
DIFFERENTIAL I/O
V_OD
'V_OD
Output Differential Voltage
V_OD Magnitude Change from
Differential LOW-to-HIGH
R_L 100 :, See Figure
R_L 100 :, See Figure
150
225
350
mV
15.0
mV
V_OS
'V_OS
Offset Voltage
Offset Magnitude Change from
Differential LOW-to-HIGH
R_L 100 :, See Figure
V_DD 2.775 r 5%
925
mV
15.0
mV
I_OS
Short Circuit Output Current
V_OUT 0V
(Note 4)
Driver Enabled
Driver Disabled
2.5
5.0
mA
r5.0
PA
I_OZ
V_TH
V_TL
V_ICM
R_TRM0
Disabled Output Leakage Current DP 0V to V_DDP, DIRI V_DDP
Differential Input Threshold HIGH See Figure 12 and Table 2
Differential Input Threshold LOW See Figure 12 and Table 2
Input Common Mode Range
CKSI Internal Receiver
Termination Resistor
DS I/O Termination Resistor
V_DD 2.775 r 5%
V_ID 225 mV, V_IC 925 mV, DIRI 0
|CKSI^  CKSI^| V_ID
V_ID 225 mV, V_IC 925 mV, DIRI 0
|DS^  DSI^| V_ID
r1.0
r10.0
PA
100
mV
100
mV
300
925
1550
mV
80.0
100
120
:
80.0
100
120
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