FAB2210 Datasheet, PDF (7/35 Pages) Fairchild Semiconductor – Audio Subsystem with Class-G Headphone and 3.3W Mono Class-D Speaker with Dynamic Range Compression

I²C DC Electrical Characteristics
Unless otherwise noted, SV_DD=2.8V to 5.25V, DV_DD=1.6V to 2.8V, T_A=-40°C to 85°C.
Symbol
Parameter
V_IL Low-Level Input Voltage
V_IH High-Level Input Voltage
V_OL
Low-Level Output Voltage at 3mA Sink Current
(Open-Drain or Open-Collector)
I_IH
High-Level Input Current of Each I/O Pin, Input Voltage=V_SVDD
I_IL
Low-Level Input Current of Each I/O Pin, Input Voltage=0V
Fast Mode (400kHz)
Min.
Max.
Unit
-0.3
0.6
V
1.3
V
0
0.4
V
-1
1
µA
-1
1
µA
I²C AC Electrical Characteristics
Unless otherwise noted, SV_DD=2.8V to 5.25V, DV_DD=1.6V to 2.8V, T_A=-40°C to 85°C.
Symbol
Parameter
Fast Mode (400kHz)
Min.
Max.
Unit
f_SCL SCL Clock Frequency
0
400
kHz
t_HD;STA
t_LOW
Hold Time (Repeated) START Condition
Low Period of SCL Clock
0.6
µs
1.3
µs
t_HIGH
t_SU;STA
High Period of SCL Clock
Set-up Time for Repeated START Condition
0.6
µs
0.6
µs
t_HD;DAT
t_SU;DAT
t_r
t_f
Data Hold Time
Data Set-up Time⁽⁴⁾
Rise Time of SDA and SCL Signals⁽⁵⁾
Fall Time of SDA and SCL Signals⁽⁵⁾
0
0.9
µs
100
ns
20+0.1C_b
300
ns
20+0.1C_b
300
ns
t_SU;STO Set-up Time for STOP Condition
0.6
µs
t_BUF Bus-Free Time between STOP and START Conditions
1.3
µs
t_SP Pulse Width of Spikes that Must Be Suppressed by the Input Filter
0
50
ns
Notes:
4. A Fast-Mode I²C-Bus® device can be used in a Standard-Mode I²C-Bus system, but the requirement t_SU;DAT
≥250ns must then be met. This is automatically the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the
Serial Data (SDA) line t_{r_max} + t_SU;DAT=1000 + 250=1250ns (according to the Standard-Mode I²C Bus specification)
before the SCL line is released.
5. C_b equals the total capacitance of one bus line in pf. If mixed with High-Speed Mode devices, faster fall times are
allowed according to the I²C specification.
Figure 3. Definition of Timing for Full-Speed Mode Devices on the I²C Bus
© 2011 Fairchild Semiconductor Corporation
FAB2210 • Rev. 1.1.1
7
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