FAB2210 Datasheet, PDF (14/35 Pages) Fairchild Semiconductor – Audio Subsystem with Class-G Headphone and 3.3W Mono Class-D Speaker with Dynamic Range Compression

Headphone Amplifier High-Impedance Mode
The FAB2210 headphone outputs are placed in a High-
Impedance Mode by setting the HP_HIZ bit to 1 and
turning off the headphone amplifier. This can be useful if
the system’s headphone jack is shared with other
devices. For proper high-impedance operation, SRST
must be set to 0 and the headphone amplifier must be
off (see HP_MONO, HPAMIX, and HP_BMIX register
definitions). Voltages on the HOUTL and HOUTR pins
must not exceed DVDD and must not be below -DVDD.
Headphone Volume Ramp and Zero
Crossing Detection
The HP_SVOFF and HP_ZCSOFF bits control the
headphone volume when HP_ATT is changed.
HP_SVOFF and HP_ZCSOFF do not slow down turn-on
or turn-off when using the HP_AMIX, HP_BMIX, or
SRST bits. Thermal shutdown conditions are not slowed
by HP_SVOFF or HP_ZCSOFF.
Table 1. Headphone Volume-Change Behavior
HP_SVOFF HP_ZCSOFF Behavior when HP_ATT is Changed
1
1
Volume changes immediately.
For each channel, wait until a zero crossing occurs in the input before changing
1
0
volume. If a zero crossing does not occur within 200µs, volume is forced to the new
setting.
0
1
Volume is ramped to the new setting at a rate of 200µs per step.
Volume is changed by one step when a zero crossing occurs. If a zero crossing does
0
0
not occur within 200µs, a step is forced. Only the first zero crossing within 200µs
triggers a volume change; volume does not change again until the next 200µs.
Headphone Amplifier Noise Gate
The headphone noise gate automatically reduces the
headphone volume when its input amplitudes are low to
reduce noise during inactivity. (This function is more
useful for speech than music.) The amplitude is
measured after input preamplifiers, but before the
headphone volume control. The headphone noise gate’s
threshold level is set by the HP_NG_RAT register. The
amplitudes of both channels must be less than the noise
gate threshold for the hold-time determined by the
NG_ATRT register.
The amount of volume reduction is set by the
HP_NG_ATT register. The speed at which the volume is
reduced is determined by the attack time setting in the
NG_ATRT register. When the volume is reduced by the
noise gate, the HP_ATT register’s readback value
remains unchanged. An internal register keeps track of
the actual volume setting.
If either headphone channel’s amplitude goes above the
headphone noise gate threshold, headphone volume is
raised back to the HP_ATT value at a rate determined
by the release time setting in the NG_ATRT register. If
HP_MONO=1, only left channel amplitude is monitored.
To avoid unpredictable behavior, noise gate settings
should not change while the headphone amplifier is on.
Class-D Speaker Amplifier
The FAB2210 utilizes a “Filterless” modulation scheme
to achieve 92% efficiency, extending battery life and
reducing component count. The pulse-width modulated,
differential outputs of the Class-D amplifier switch at
300kHz. When an audio input signal is not present, the
Class-D outputs switch in-phase at 50% duty cycle,
minimizing idle current and saving power.
Programmable Spread Spectrum
Modulation
Spread spectrum modulation is employed to reduce EMI
generated at the Class-D amplifier outputs. Spread
spectrum modulates the Class-D amplifier’s switching
frequency by a programmable percentage centered
around the base switching frequency of 300kHz,
dispersing the spectral energy of the switching
waveform over a wider band. This significantly reduces
the amount of concentrated spectral energy at multiples
of the switching frequency that fixed-frequency Class-D
amplifiers emit. Spread spectrum modulation eliminates
the need for output filters, as long as the distance from
the Class-D amplifier outputs to the speaker transducer
is kept short.
Edge Rate Control (ERC)
The Edge Rate Control (ERC) circuit minimizes EMI
generated by the high-current switching waveform of the
Class-D amplifier output. One of the main contributors
to EMI generated by Class-D amplifiers is the high-
frequency energy produced by rapid (large dV/dt)
transitions at the edges of the switching waveform. The
ERC circuit suppresses the high-frequency component
of the switching waveform by extending the rise and fall
times of the output FET transitions, without
compromising efficiency and THD+N performance. Rise
and fall times are set to approximately 20ns per
transition at all power levels.
© 2011 Fairchild Semiconductor Corporation
FAB2210 • Rev. 1.1.1
14
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