FAB2210 Datasheet, PDF (15/35 Pages) Fairchild Semiconductor – Audio Subsystem with Class-G Headphone and 3.3W Mono Class-D Speaker with Dynamic Range Compression

Dynamic Range Compression (DRC)
The speaker amplifier’s DRC can be used to limit output
amplitude and reduce clipping even as the supply
voltage varies. The DRC allows high gain settings while
preventing distortion and speaker damage. This results
in louder speaker playback without increasing the
maximum peak amplitude of the speaker signal path.
To avoid unpredictable behavior, DRC settings should
not be changed while the speaker amplifier is on.
Figure 25 shows the speaker amplifier’s target output
amplitude with respect to the DRC’s input amplitude
when programmed at various Class-D output gain
settings. The DRC’s input amplitude is measured after
the speaker volume control, but before the speaker
amplifier block.
The DRC has three regions of operation: linear,
compression, and limiter. When the output amplitude is
initially low, the DRC operates in the linear region and
does not apply any gain changes to the signal. The
volume control remains fixed at the level defined in
SP_ATT. When the output amplitude has increased
above the dynamic range compression threshold, the
DRC reduces the gain of SP_ATT, thereby applying
compression to the output signal.
The compression region is defined by the compression
ratio and the dynamic range compression threshold.
The dynamic range compression threshold is set by the
DPLT register. The dynamic range compression
threshold is set 8dB below the DPLT threshold level.
The DRC applies a 2:1 compression ratio for output
signals between the dynamic range compression
threshold and limiter threshold. In the compression
region; for every 2dB rise of input amplitude, the target
output amplitude only rises by 1dB. This continues until
the output amplitude has increased above the DRC
limiter threshold.
The limiter region is defined by the DALC and DPLT
registers. In the limiter region, the target output
amplitude does not increase with the input amplitude.
The DPLT register sets an output voltage limit
independent of the battery voltage. This is useful for
speaker protection. The DALC register defines an
output voltage limit that is a percentage of the battery
voltage. Since the battery voltage sets the maximum
output amplitude, the DALC register is used as a
distortion limiter by setting the allowed clipping amount.
The DRC limiter threshold is defined as the lower of the
two limiter voltages set by the DPLT and DALC settings.
For example, in Figure 27; if DPLT=111, DALC=001,
and SV_DD=4.5V_pk, the DRC limit is 3.79V_pk as defined by
DPLT. However, if SV_DD falls to 3.0V, the DRC limiter
threshold falls to 2.7V_pk, as defined by DALC.
The speed at which gain is changed is regulated by the
attack and release settings in the DATRT register.
Figure 28 shows DRC attack and release behavior.
DRC attack occurs when the DRC determines that, for
given input amplitude, the actual output amplitude is
higher than the target output amplitude and attack
speed (defined in the DATRT register) is not to be
exceeded. When these criteria are met, volume is
reduced by one step.
DRC release occurs when the DRC determines that, for
a given input amplitude, the actual output amplitude is
lower than the target output amplitude and release
speed (defined in the DATRT register) is not be
exceeded. When these criteria are met, volume is
increased by one step.
When the volume is changed by the DRC, the SP_ATT
register readback value remains unchanged. An internal
register keeps track of the actual volume setting.
When 2:1 compression is enabled, the overall gain of the
speaker amplifier path is increased by 6dB, as shown in
Figure 26.
15
11.57
10
DRC Limiter Threshold (DPLT Limiter = 3.79Vpk and DALC Limiter off)
8dB ^{Compression Region}
5
3.57 _{DRC Compressor Threshold}
0 _{Linear Region}
Limiter Region
‐5
‐10
‐15
‐20
‐25
‐30
‐35
‐40
‐40
‐35
‐30
‐25
‐20
‐15
‐10
‐5
0
5
10
15
INPUT LEVEL (dBV_pk)
Figure 25. Dynamic Range Compression
Response vs. Class-D Output Gain Settings
15
12.46
VSVDD = 4.2V Clip Threshold (DPLT Limiter Off, DALC Limiter Off)
10
Compression Region
5
3.57 _{DRC Compressor Threshold}
0
Linear Region
‐5
‐10
‐15
‐20
‐25 ^6dB
‐30
‐35
‐40
‐40
‐35
‐30
‐25
‐20
‐15
‐10
‐5
0
5
10
15
INPUT LEVEL (dBV_pk)
Figure 26. Gain Boost when Enabling DRC
© 2011 Fairchild Semiconductor Corporation
FAB2210 • Rev. 1.1.1
15
www.fairchildsemi.com