FAB2210 Datasheet, PDF (16/35 Pages) Fairchild Semiconductor – Audio Subsystem with Class-G Headphone and 3.3W Mono Class-D Speaker with Dynamic Range Compression

5
4.5
4
DPLT
3.5
AGC Limit
3
2.5
2
2.5
3
3.5
4
4.5
5
5.5
SVDD (V)
Figure 27. DRC Limiter Threshold when
DPLT=3.79V_pk (111) and DALC=0.9*SVDD (001)
Start
Reset the timers.
yes
Does the actual
output amplitude match
the target output
amplitude?
no
yes
no
Has enough
time (attack speed)
passed since the last
gain change?
yes
Is the
actual output
amplitude above
the target output
Amplitude?
no
Has enough
time (decay speed)
no
passed since the last
gain change?
yes
Reduce gain by
1 step
Increase gain by
1 step.
Figure 28. DRC Flowchart
© 2011 Fairchild Semiconductor Corporation
FAB2210 • Rev. 1.1.1
16
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