74F433 Datasheet, PDF (7/16 Pages) Fairchild Semiconductor – First-In First-Out (FIFO) Buffer Memory

positions of bits in an expanded 74F433 FIFO resulting
from a 2032-bit serial bit train.
Interlocking Circuitry—Most conventional FIFO designs
provide status signal analogous to IRF and ORE. However,
when these devices are operated in arrays, variations in
unit-to-unit operating speed require external gating to
ensure that all devices have completed an operation. The
74F433 incorporates simple but effective 'master/slave'
interlocking circuitry to eliminate the need for external gat-
ing.
In the 74F433 array of Figure 6, devices 1 and 5 are the
row masters; the other devices are slaves to the master in
their rows. No slave in a given row initializes its input regis-
ter until it has received a LOW on its IES input from a row
master or a slave of higher priority.
Similarly, the ORE outputs of slaves do not go HIGH until
their inputs have gone HIGH. This interlocking scheme
ensures that new input data may be accepted by the array
when the IRF output of the final slave in that row goes
HIGH and that output data for the array may be extracted
when the ORE output of the final slave in the output row
goes HIGH.
The row master is established by connecting its IES input
to ground, while a slave receives its IES input from the IRF
output of the next-higher priority device. When an array of
74F433 FIFOs is initialized with a HIGH on the MR inputs
of all devices, the IRF outputs of all devices are HIGH.
Thus, only the row master receives a LOW on the IES input
during initialization.
Figure 10 is a conceptual logic diagram of the internal cir-
cuitry that determines master/slave operation. When MR
and IES are LOW, the master latch is set. When TTS goes
LOW, the initialization flip-flop is set. If the master latch is
HIGH, the input register is immediately initialized and the
initialization flip-flop reset. If the master latch is reset, the
input register is not initialized until IES goes LOW. In array
operation, activating TTS initiates a ripple input register ini-
tialization from the row master to the last slave.
A similar operation takes place for the output register.
Either a TOS or TOP input initiates a load-from-stack oper-
ation and sets the ORE request flip-flop. If the master latch
is set, the last output register flip-flop is set and the ORE
line goes HIGH. If the master latch is reset, the ORE output
is LOW until a Serial Output Enable (OES) input is
received.
FIGURE 5. A Horizontal Expansion Scheme
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