74F433 Datasheet, PDF (12/16 Pages) Fairchild Semiconductor – First-In First-Out (FIFO) Buffer Memory

AC Operating Requirements
Symbol
Parameter
t_S(H)
t_S(L)
t_H(H)
t_H(L)
t_S(L)
Setup Time, HIGH or LOW
D_S to Negative CPSI
Hold Time, HIGH or LOW
D_S to CPSI
Setup Time, LOW TTS to IRF,
Serial or Parallel Mode
t_S(L)
t_S(L)
t_S(L)
t_S(H)
t_S(L)
t_H(H)
t_H(L)
t_W(H)
t_W(L)
t_W(H)
t_W(L)
Setup Time, LOW Negative-Going
ORE to Negative-Going TOS
Setup Time, LOW Negative-Going
IES to CPSI
Setup Time, LOW Negative-Going
TTS to CPSI
Setup Time, HIGH or LOW
Parallel Inputs to PL
Hold Time, HIGH or LOW
Parallel Inputs to PL
CPSI Pulse Width
HIGH or LOW
PL Pulse Width, HIGH
TTS Pulse Width, LOW
Serial or Parallel Mode
t_W(L)
t_W(H)
t_W(L)
t_W(H)
t_W(L)
t_REC
MR Pulse Width, LOW
TOP Pulse Width
HIGH or LOW
CPSO Pulse Width
HIGH or LOW
Recovery Time
MR to Any Input
T_A = +25°C
V_CC = +5.0V
Min
Max
7.0
7.0
2.0
2.0
0.0
0.0
8.0
30.0
0.0
0.0
4.0
4.0
10.0
5.0
7.0
7.0
7.0
14.0
7.0
14.0
7.0
8.0
T_A = 0°C to +70°C
V_CC = +5.0V
Min
Max
7.0
7.0
2.0
2.0
0.0
0.0
9.0
33.0
0.0
0.0
4.0
4.0
11.0
6.0
9.0
9.0
9.0
16.0
7.0
16.0
7.0
15.0
Units
Figure
Number
ns
Figure 11
Figure 12
Figure 11
ns
Figure 12
Figure 17
Figure 18
ns
Figure 13
Figure 14
ns
Figure 12
ns
ns
Figure 11
Figure 12
ns
Figure 17
Figure 18
Figure 11
ns
Figure 12
Figure 13
Figure 14
ns
Figure 16
ns
Figure 15
Figure 13
ns
Figure 14
ns
Figure 16
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