74F433 Datasheet, PDF (4/16 Pages) Fairchild Semiconductor – First-In First-Out (FIFO) Buffer Memory

FIGURE 2. Final Positions in an 74F433
Resulting from a 256-Bit Serial Train
Fall-Through Stack—The outputs of flip-flops F₀–F₃ feed
the stack. A LOW level on the Transfer to Stack (TTS) input
initiates a fall-through action; if the top location of the stack
is empty, data is loaded into the stack and the input register
is re-initialized. (Note that this initialization is delayed until
PL is LOW). Thus, automatic FIFO action is achieved by
connecting the IRF output to the TTS input.
An RS-type flip-flop (the initialization flip-flop) in the control
section records the fact that data has been transferred to
the stack. This prevents multiple entry of the same word
into the stack even though IRF and TTS may still be LOW;
the initialization flip-flop is not cleared until PL goes LOW.
Once in the stack, data falls through automatically, pausing
only when it is necessary to wait for an empty next location.
In the 74F433, the master reset (MR) input only initializes
the stack control section and does not clear the data.
Output Register
The Output Register (see Figure 3) receives 4-bit data
words from the bottom stack location, stores them, and out-
puts data on a 3-STATE, 4-bit parallel data bus or on a 3-
STATE serial data bus. The output section generates and
receives the necessary status and control signals.
Parallel Extraction—When the FIFO is empty after a LOW
pulse is applied to the MR input, the Output Register Empty
(ORE) output is LOW. After data has been entered into the
FIFO and has fallen through to the bottom stack location, it
is transferred into the output register, if the Transfer Out
Parallel (TOP) input is HIGH. As a result of the data trans-
fer, ORE goes HIGH, indicating valid data on the data out-
puts (provided that the 3-STATE buffer is enabled). The
TOP input can then be used to clock out the next word.
When TOP goes LOW, ORE also goes LOW, indicating
that the output data has been extracted; however, the data
itself remains on the output bus until a HIGH level on TOP
permits the transfer of the next word (if available) into the
output register. During parallel data extraction, the serial
output clock (CPSO) line should be LOW. The Transfer Out
Serial (TOS) line should be grounded for single-slice oper-
ation or connected to the appropriate ORE line for
expanded operation (refer to the “Expansion” section).
The TOP signal is not edge-triggered. Therefore, if TOP
goes HIGH before data is available from the stack but data
becomes available before TOP again goes LOW, that data
is transferred into the output register. However, internal
control circuitry prevents the same data from being trans-
ferred twice. If TOP goes HIGH and returns to LOW before
data is available from the stack, ORE remains LOW, indi-
cating that there is no valid data at the outputs.
Serial Extraction—When the FIFO is empty after a LOW
is applied to the MR input, the ORE output is LOW. After
data has been entered into the FIFO and has fallen through
to the bottom stack location, it is transferred into the output
register, if the TOS input is LOW and TOP is HIGH. As a
result of the data transfer, ORE goes HIGH, indicating that
valid data is in the register.
The 3-STATE Serial Data Output (Q_S) is automatically
enabled and puts the first data bit on the output bus. Data
is serially shifted out on the HIGH-to-LOW transition of
CPSO. To prevent false shifting, CPSO should be LOW
when the new word is being loaded into the output register.
The fourth transition empties the shift register, forces ORE
LOW, and disables the serial output, Q_S. For serial opera-
tion, the ORE output may be tied to the TOS input, request-
ing a new word from the stack as soon as the previous one
has been shifted out.
Expansion
Vertical Expansion—The 74F433 may be vertically
expanded, without external components, to store more
words. The interconnections necessary to form a 190-word
by 4-bit FIFO are shown in Figure 4. Using the same tech-
nique, any FIFO of (63n+1)-words by 4-bits can be config-
ured, where n is the number of devices. Note that
expansion does not sacrifice any of the 74F433 flexibility
for serial/parallel input and output.
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