FAN54013_12 Datasheet, PDF (33/36 Pages) Fairchild Semiconductor – FAN54010 / FAN54011 / FAN54012 / FAN54013 / FAN54014

Table 23. Register Bit Definitions
This table defines the operation of each register bit for all IC versions. Default values are in bold text.
Bit
Name
Value Type
Description
1 HZ_MODE
0
R/W Not High-Impedance Mode
1
High-Impedance Mode
0 OPA_MODE
0
R/W Charge Mode
1
Boost Mode
See Table 16
OREG
7:2
OREG
1
OTG_PL
Register Address: 02
Default Value=0000 1010 (0AH)
R/W
Charger output “float” voltage; programmable from 3.5 V to 4.44 V in 20 mV
increments; defaults to 000010 (3.54 V), see Table 3
0
R/W OTG pin active LOW
1
OTG pin active HIGH
0
OTG_EN
0
R/W Disables OTG pin
1
Enables OTG pin
IC_INFO
7:5 Vendor Code 100
4:2
PN
1:0
REV
00
Register Address: 03 or 3B
Default Value=100X X100
R Identifies Fairchild Semiconductor as the IC supplier
R Part number bits, see the Ordering Info on page 1
R IC Revision, revision 1.X, where X is the decimal of these three bits
IBAT
7
6:4
3
2:0
RESET
IOCHARGE
Reserved
ITERM
1
Table 5
1
Table 6
Register Address: 04
Default Value=1000 1001 (89H)
W
Writing a 1 resets charge parameters, except the Safety register (Reg6), to their
defaults: writing a 0 has no effect; read returns 1
R/W Programs the maximum charge current, see Table 5
R Unused
R/W Sets the current used for charging termination, see Table 6
SP_CHARGER (FAN54013-14)
7
Reserved
0
6 DIS_VREG
0
1
0
5
IO_LEVEL
1
0
4
SP
1
0
3 EN_LEVEL
1
2:0
VSP
Table 8
Register Address: 05
Default Value=001X X100
R Unused
R/W 1.8 V regulator is ON
1.8 V regulator is OFF
R/W Output current is controlled by IOCHARGE bits
Voltage across R_SENSE for output current control is set to 22.1 mV (325 mAfor
R_SENSE=68 m, 221 mA for 100 m)
R Special charger is not active (V_BUS is able to stay above V_SP)
Special charger has been detected and V_BUS is being regulated to V_SP
R DISABLE pin is LOW
DISABLE pin is HIGH
R/W Special charger input regulation voltage, see Table 8
SAFETY (FAN54013-14)
7
Reserved
0
6:4
ISAFE
Table 9
3:0
VSAFE Table 10
MONITOR
7 ITERM_CMP
6 VBAT_CMP
5
LINCHG
Table 19
Register Address: 06
Default Value=0100 0000 (40H)
R Bit disabled and always returns 0 when read back
R/W Sets the maximum I_OCHARGE value used by the control circuit, see Table 9
R/W Sets the maximum V_OREG used by the control circuit, see Table 10
Register Address: 10H (16)
See Table 19
R ITERM comparator output, 1 when VRSENSE > ITERM reference
R Output of VBAT comparator
R 30 mA linear charger ON
© 2011 Fairchild Semiconductor Corporation
FAN5401X Family • Rev. 1.0.4
33
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