FAN54013_12 Datasheet, PDF (31/36 Pages) Fairchild Semiconductor – FAN54010 / FAN54011 / FAN54012 / FAN54013 / FAN54014

Read and Write Transactions
The figures below outline the sequences for data read and
write. Bus control is signified by the shading of the packet,
defined as ^{Master Drives Bus} and
All addresses and data are MSB first.
Slave Drives Bus _.
Table 21. Bit Definitions for Figure 49, Figure 50
Symbol
Definition
S START, see Figure 46.
A
ACK. The slave drives SDA to 0 to acknowledge
the preceding packet.
A
NACK. The slave sends a 1 to NACK the
preceding packet.
R Repeated START, see Figure 48
P STOP, see Figure 47
7 bits
0
8 bits
0
S Slave Address 0 A
Reg Addr
A
8 bits
Data
Figure 49. Write Transaction
0
AP
7 bits
0
S Slave Address 0 A
8 bits
Reg Addr
0
7 bits
0
A R Slave Address 1 A
Figure 50. Read Transaction
8 bits
Data
1
AP
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FAN5401X Family • Rev. 1.0.4
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