FAN5069_08 Datasheet, PDF (18/22 Pages) Fairchild Semiconductor – PWM and LDO Controller Combo

Design Tools
Fairchild application note AN-6010 provides a PSPICE
model and spreadsheet calculator for the PWM regula-
tor, simplifying external component selections and verify-
ing loop stability. The topics covered provide an
understanding of the calculations in the spreadsheet.
The spreadsheet calculator, which is part of AN-6010,
can be used to calculate all external component values
for designing around FAN5069. The spreadsheet pro-
vides optimized compensation components and gener-
ates a Bode Plot to ensure loop stability.
Based on the input values entered, AN-6010’s PSPICE
model can be used to simulate Bode Plots (for loop sta-
bility) as well as transient analysis to help customize the
design for a wide range of applications.
Use Fairchild Application Note AN-6005 for prediction of
the losses and die temperatures for the power semicon-
ductors used in the circuit.
AN-6010 and AN-6005 can be downloaded from
www.fairchildsemi.com/apnotes/.
Layout Considerations
The switching power converter layout needs careful
attention and is critical to achieving low losses and clean
and stable operation. Below are specific recommenda-
tions for good board layout:
■ Keep the high-current traces and load connections as
short as possible.
■ Use thick copper boards whenever possible to
achieve higher efficiency.
■ Keep the loop area between the SW node, low-side
MOSFET, inductor, and the output capacitor as small
as possible.
■ Route high dV/dt signals, such as SW node, away
from the error amplifier input/output pins. Keep com-
ponents connected to these pins close to the pins.
■ Place ceramic de-coupling capacitors very close to the
VCC pin.
■ All input signals are referenced with respect to AGND
pin. Dedicate one layer of the PCB for a GND plane.
Use at least four layers for the PCB.
■ Minimize GND loops in the layout to avoid EMI-related
issues.
■ Use wide traces for the lower gate drive to keep the
drive impedances low.
■ Connect PGND directly to the lower MOSFET source
pin.
■ Use wide land areas with appropriate thermal vias to
effectively remove heat from the MOSFETs.
■ Use snubber circuits to minimize high-frequency ring-
ing at the SW nodes.
■ Place the output capacitor for the LDO close to the
source of the LDO MOSFET.
© 2005 Fairchild Semiconductor Corporation
FAN5069 Rev. 1.1.5
18
www.fairchildsemi.com